Commit Graph

6 Commits

Author SHA1 Message Date
Yonghua Huang
a2bffc7630 hv: pass-through xsave feature to guests
enable Xsave feature and pass-through it to guests
 update based on v2:
  - enable host xsave before expose it to guests.
  - add validation for the value to be set to 'xcr0' before call xsetbv
    when handling xsetbv vmexit.
  - tested in SOS guest, created two threads to do different
    FP calculations,test code runs in user land of sos.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-03 17:50:27 +08:00
Rusty Lynch
504d1f9d28 Fix compiler warnings when building for UEFI
Signed-off-by: Rusty Lynch <rusty.lynch@intel.com>
2018-03-28 09:28:24 +08:00
Li, Fei1
bf1a312fa6 Add cpuinfo_x86 to cache cpu capability/feature
Add a global boot_cpu_data to cache common cpu capbility/feature
for detect cpu capbility/feature.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-03-23 08:03:11 +00:00
Yonghua Huang
0a5806ea8e hv:enable APICv features based on CPU capability
this patch is to detect and enable only APICv features which
are actually supported by the processor, instead fo tuning on
all features by default.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-03-21 15:34:25 -07:00
Mingqiang Chi
67871c42ea Add page mask MACRO
Add 'CPU_PAGE_MASK' used for calculate address,
Change IA32E_REF_MASK from 0x7ffffffffffff000 to 0x000ffffffffff000
for MMU/EPT entry, bit62:52(ignore) bit63(VE/XD)
if we want to obtain the address from the MMU/EPT entry,need to clear
bit63:52 by IA32E_REF_MASK

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-03-20 14:19:41 +08:00
Eddie Dong
f4cd4338fd initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 21:05:38 +08:00