Haicheng Li
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bd0e83fa5f
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io: add risc-v mmio read and write APIs with memory order
Follow multi-arch, add risc-v MMIO APIs with memory order, without
PIO support.
Tracked-On: #8807
Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com>
Co-developed-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
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2025-10-09 17:15:06 +08:00 |
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