For data structure types "struct vm", its name is identical
with variable name in the same scope. This is a MISRA C violation.
Naming convention rule:If the data structure type is used by multi
modules, its corresponding logic resource is exposed to external
components (such as SOS, UOS), and its name meaning is simplistic
(such as vcpu, vm), its name needs prefix "acrn_".
The following udpates are made:
struct vm *vm-->struct acrn_vm *vm
Tracked-On: #861
Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
For data structure types "struct vcpu_arch", its name
shall follow Naming convention.
Naming convention rule:If the data structure type is
used by multi modules, its corresponding logic resource
is exposed to external components (such as SOS, UOS),
and its name meaning is simplistic (such as vcpu, vm),
its name needs prefix "acrn_". Variable name can be
shortened from its data structure type name.
The following udpates are made:
struct vcpu_arch arch_vcpu-->struct acrn_vcpu_arch arch
Tracked-On: #861
Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
For data structure types "struct vcpu", its name is identical
with variable name in the same scope. This is a MISRA C violation.
Naming convention rule:If the data structure type is used by multi
modules, its corresponding logic resource is exposed to external
components (such as SOS, UOS), and its name meaning is simplistic
(such as vcpu, vm), its name needs prefix "acrn_".
The following udpates are made:
struct vcpu *vcpu-->struct acrn_vcpu *vcpu
Tracked-On: #861
Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
The /dev/vbs_ipu is used as the backend driver of IPU mediator on SOS kernel.
If the file of /dev/vbs_ipu exists, it indicates that IPU works in mediator mode.
Other it will fall back to the pass-through mode.
Tracked-on: https://github.com/projectacrn/acrn-hypervisor/issues/1373
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Currently vpci treats IO port CF9 as a regular PCI CONFIG_ADDRESS port,
so that SOS can't do system reboot through port CF9.
This patch handles port CF9 in this way:
- SOS (vm0): it is allowed to actually access the physical IO port for byte
accesses.
- UOS (non-vm0) or partitioning guests: any accesses to port CF9 are
ignored.
Tracked-On: #1568
Signed-off-by: Zide Chen zide.chen@intel.com
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
paddr_guest2host has same function with dm_gpa2hva. And There is no
usage of dm_gpa2hva. Remove it.
Tracked-On: #1595
Signed-off-by: Shuo Liu <shuo.a.liu@intel.com>
Acked-by: Fengwei Yin <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This patch adds ioreq.h to the input of doxygen and replaces hard-coded API docs
with doxygen-generated ones.
Tracked-On: #1595
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch adds more comments to describe the structures and functions that are
public to the other components in the hypervisor. The comments are in
doxygen-style for document generation.
v2 -> v3:
* Reformat the flow in the doc for vhm_io_request.
v1 -> v2:
* Fix typos and inconsistencies in the comments.
* Wrap the text-based diagram in the doc for vhm_request in @verbatim
Tracked-On: #1595
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Unmap the trusty EPT mapping when destroy_secure_world. The reason is
now the normal world and trusty will share the PD and PT page. Before
we add the mapping for each world, we should unmap it from another world.
Besides, fix a minor bug for condition priority.
Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
MMIO registers might be changed at any time.
The changes might not be catched due to compiler optimization
if there is no 'volatile' keyword.
We have defined MMIO read/write APIs to address the above issue.
'volatile' keyword is being used in these defined MMIO read/write
APIs.
This patch updates the MMIO registers access implementation in
'msix.c' to use these defined MMIO read/write APIs.
v1 -> v2:
* update the algorithm to get the address of high 32-bit of
'pentry->addr'
- previous way:
&(pentry->addr) + 4U
===> &(pentry->addr) + 4 * 64 bits
since 'pentry->addr' is 64 bits
- new way:
(char *)&(pentry->addr) + 4U
===> &(pentry->addr) + 4 * 8 bits
since 'char' is 8 bits
Tracked-On: #1711
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
function sscanf is banned according to the security
requirements. So remove sscanf api.
Tracked-On: #1254
Signed-off-by: Tianhua Sun <tianhuax.s.sun@intel.com>
Reviewed-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Tao, Yuhong <yuhong.tao@intel.com>
1, remove unsafe function sscanf
2, replace strlen with strnlen
3, replace atoll with strtoll and replace aoti with strtol
Tracked-On: #1254
Signed-off-by: Tianhua Sun <tianhuax.s.sun@intel.com>
Acked-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Tao, Yuhong <yuhong.tao@intel.com>
Getting Started Guide: add one more bundle to be added on a Clear
Linux development machine to make sure 'make' and other development
packages are available.
ACRN Documentation Generation: expand the 'PATH' variable to include
'~/.local/bin' where 'sphinx-build' is installed.
Tracked-On: #1650
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
This patch adds vtd.h to the input of doxygen and replaces hard-coded API docs
with doxygen-generated ones.
Tracked-On: #1595
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
This patch adds more comments to describe the structures and functions of vtd
that are public to the other components in the hypervisor. The comments are in
doxygen-style for document generation.
Tracked-On: #1595
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
The patch adds related head files to the input of doxygen and
replaces hard-code API docs with doxygen-generated ones.
v1-->v2:
Put the 'kerneldoc' back.
V2-->V3:
Rebase
Tracked-On: #1595
Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
This patch adds more comment to describe functions that are
interfaces to the other modules in the hypervisor. The comments
are in doxygen-style for document generation.
V1-->V2:
Rebase
Tracked-On: #1595
Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
This patch adds comments to the main public functions
of vCPU in the hypervisor. The comments are in doxygen-style
for document generation.
Tracked-On: #1595
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Convert line endings setting for l1tf.rst doc
from windows style to unix style.
Tracked-On: #1672
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
ACRN, in partition mode, supports LAPIC pass-thru to guests. Guest needs
to use x2APIC mode of LAPIC for pass-thru to be enabled.
ACRN also needs the user to configure lapic_pt to true in vm_desc
for the VM.
Interrupt Command Register (ICR) is the only APIC register that is
intercepted. Reference code in partition/vm_description.c enables
LAPIC pass-thru for vm2.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
ACRN does not support platforms that do not have x2APIC mode of LAPIC
in hardware. With this patch, x2APIC is exposed to guests by default.
Extended Topology Leaf 0xb in cpuid returns x2APIC ID and topology
information to OS. This patch adds support to return guest topology
and guest x2APIC ID. Number of SMT siblings is returned as 0.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
This patch adds support for self-IPI virtualization when guest
uses vLAPIC in x2APIC mode.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
When guest switches from xAPIC mode to x2APIC mode of vLAPIC operation,
MSRs are used to access vLAPIC. This patch adds APICv support for
MSR accesses to vLAPIC. Switching from xAPIC to x2APIC is supported via
APIC BASE MSR. Other modifications like disabling and switching back to
xAPIC are not supported.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
This patch adds support to return APIC ID if guest uses vLAPIC
in x2APIC mode.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
This patch converts x2APIC MSR accesses to corresponding LAPIC MMIO offset to
utitlize vlapic_write/read APIs to virtualize LAPIC. Also adds support to inject
GP fault when read-only registers are attempted to be written to or vice versa.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
When guest uses vLAPIC in x2APIC mode, ICR write is a single MSR write.
Also, the destination field for device interrupts and IPIs should not be
handled in the same way as xAPIC mode. This patch adds support for x2APIC
mode operation of guest vLAPIC.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
x2APIC ID and LDR are in different format compared to xAPIC mode of operation.
This patch adds code to build ID and LDR when guest uses vLAPIC in x2APIC mode.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
Extending enable_msr_interception to accept mode as input. Mode specifies
if the API user wants ACRN to intercept on read-only or write-only or both
read and write or disable MSR interception altogether.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
Accessing x2APIC MSRs in xAPIC mode should result in GP exception according
to SDM section 10.12.2. Adding support to ACRN to inject GP into guests for
the same reason.
Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
(EV_MSC, MSC_TIMESTAMP) is added to each frame just before the
SYN event since kernel 4.15. EV_MSC is configured as
INPUT_PASS_TO_ALL. In the use case of virtio-input, there is
a loop as follows:
- A mt frame with (EV_MSC, MSC_TIMESTAMP) is passed to FE.
- FE will call virtinput_status to pass (EV_MSC, MSC_TIMESTAMP)
back to BE.
- BE writes this event to evdev. Because (EV_MSC, MSC_TIMESTAMP)
is configured as INPUT_PASS_TO_ALL, it will be written into
the event buffer of evdev then be read out by BE without
SYN followed.
- Each mt frame will introduce one (EV_MSC, MSC_TIMESTAMP).
Later the frame becomes larger and larger...
This patch fixed above issue by ignoring MSC_TIMESTAMP from guest.
Besides that timestamp is added for every status event from guest
before writing to evdev.
Tracked-On: #1670
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
In the C99 standard, the order of evaluation associated with multiple #,
multiple ## or a mix of # and ## preprocessor operator is unspecifie.
So it is unsafe to use multiple # or ## in a macro.
Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Normal world would also setup 511 GB gpa EPT mapping when initialize.
So we couldn't know which the world is from the gpa. But trusty is so
special for that we know where it would get a pml4_page or pdpt_page.
As a result, we could simpler this by just return the pml4_page or
pdpt_page to it when it needs.
Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Replace dynamic memory allocation in memory management with static memory allocation.
Since the static memory allocation can guarantee the allocation never failed, so
split_large_page and construct_pgentry don't need to return a errno any more.
Besides, the destroy_ept don't need to free page any more. Instead, it would memset
the eptp to 0 to make sure we can't walk this paging table again.
Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Add static paging table allocation API for EPT.
Note: must configure SOS/UOS_REAM_SIZE exactly as the platform.
Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Add static paging table allocation API for hypervisor.
Note: must configure PLATFORM_RAM_SIZE and PLATFORM_MMIO_SIZE exactly as the platform.
Rename RAM_START/RAM_SIZE to HV_RAM_START/HV_RAM_SIZE for HV.
Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
