Commit Graph

8 Commits

Author SHA1 Message Date
Chenli Wei
6d57f8254b misc: rename common.py to avoid private library conflict
The offline tool use a utility libary and use "common" to named it, this
name conflict with some customer's local library, so we rename it to a
better and clear name.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
2022-11-14 12:03:51 +08:00
Chenli Wei
a75660be58 misc: refine the vCPU sort for cpu_affinity and CAT
The current code sort cpu list by string order, this is an issue when
we want to assign more then 10 vCPUs for some VM.

So this patch rewrite the sort of these list, now the cpu list order
by int type.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2022-08-30 16:36:53 +08:00
Chenli Wei
72c406c2b7 misc: move the RDT interface to common library
The current RDT class and interface was define by the clos.py which is
mix get and merge RDT policy, create clos nodes.

Now we need call these interface to check the CLOS IDs number after
merged RDT policy, so this patch abstract the RDT interface to common
and add an assert to check the CLOS IDs number.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2022-06-29 13:53:42 +08:00
Chenli Wei
8331375172 misc: refine CDP mode
The current code use cache type to check whether enable the CDP mode,
then merge policy by clos_mask, sometimes the data and code CLOS is not
continuous.

This patch add a special CDP policy to record and merge policy to fix
this above issue.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
2022-05-30 09:23:33 +08:00
Chenli Wei
534334852d misc: add match interface for RDT policy
The current code use a merge interface to merge policy which fix match
and merge in one function.

This patch split the merge interface and add a match interface to check
whether this policy could be merged.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
2022-05-30 09:23:33 +08:00
Chenli Wei
a1b266f807 misc: refine CLOS module for expansibility
This patch refine CLOS module by the following aspects:

1 Unified CACHE_ID type to Hex Format
2 Rewrite policy merge with RDT Class
3 Modify the logic of generate CPU mask

Signed-off-by: Chenli Wei <chenli.wei@intel.com>
2022-05-11 17:00:51 +08:00
Chenli Wei
3b4841b91d misc: fix the issue of create hv node
There was an issue of create hv node by clos module, the direct cause
is the create logic and the indirect cause is these modules of
static_allocators was not sorted before run which cause some platform
have issue and CI could not found.

So this patch fix the create issue and sorted the modules list to make
sure all these platform could work well and get the same allocation.xml

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
2022-04-28 13:42:54 +08:00
Chenli Wei
4807385fe2 misc: refine cache config
The current RDT setting requires users to calculate the CLOS mask and
the details, it is not a user-friendly setting.

So we redesigned RDT, users can easily specify the cache of each vcpu
for VMs.

This patch add an RDT region element for schema, calculate and generate
all the mask and rdt parameters by config tool to generates rdt_info
struct for board.c.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
2022-04-24 16:52:24 +08:00