Prevent allocator to allocate PCI bus mmio windows to other devices.
Tracked-On: #8191
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Added python3-tqdm depend in gen_acrn_deb.py
Tracked-On: #8155
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
Some member of CACHE_REGION have no documentation element, this cause
some issue when we generate documentation for user.
This patch add some documentation to fix the above issue.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Add a new flag in ioeventfd ioctl to support asyncio. After that, the IO
request will be processed in asyncio path by kernel and hypervisor.
Tracked-On: #8209
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
asyncio is a new mechanism in ACRN, which is special for these devices
which need high IO performance. ACRN hypervisor would process the IO
request from User VM in an async mode.
Just like the original IOReq shared page, the devicemodel also create a
page for fastio requests. As the asyncio use the ioeventfd, so the
reuqests are handled in kernel, devicemodel only need to provide the
page.
Tracked-On: #8209
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
For an IO request, hv will check if it was registered in asyncio desc
list. If yes, put the corresponding fd to the shared buffer. If the
shared buffer is full, yield the vcpu and try again later.
Tracked-On: #8209
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Add hypercall to add/remove asyncio request info. Hv will record the
info in a list, and when a new ioreq is come, hv will check if it is
in the asyncio list, if yes, queue the fd to asyncio buffer.
Tracked-On: #8209
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Current IO emulation is synchronous. The user VM need to wait for the
completion of the the I/O request before return. But Virtio Spec
introduces introduces asynchronous IO with a new register in MMIO/PIO
space named NOTIFY, to be used for FE driver to notify BE driver, ACRN
hypervisor can emulate this register by sending a notification to vCPU
in Service VM side. This way, FE side can resume to work without waiting
for the full completion of BE side response.
Tracked-On: #8209
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Extend sbuf hypercall to support other kinds of share buffer.
Tracked-On: #8209
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
sbuf is now only used for debug purpose, but later, it will be used as a
common interfaces. So, move the sbuf related code out of the debug directory.
Tracked-On: #8209
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Improve SMP call to support ACRN shell to operate RTVM.
before, the RTVM CPU can't be kicked off by notification IPI,
so some shell commands can't support it, like rdmsr/wrmsr,
memory/registers dump. So INIT will be used for RTVM, which
LAPIC is pass-thru.
Tracked-On: #8207
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
By default, notification IPI used to kick sharing pCPU, INIT
used to kick partition pCPU. If USE_INIT_IPI flag is passed to
hypervisor, only INIT will be used to kick pCPU.
Tracked-On: #8207
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
INIT signal has been used to kick off the partitioned pCPU, like RTVM,
whose LAPIC is pass-through. notification IPI is used to kick off
sharing pCPU.
Add mode_to_kick_pcpu in per-cpu to control the way of kicking
pCPU.
Tracked-On: #8207
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
The access to PCI config_space is handled in HV for Passthrough pci
devices. And it also provides one mechanism to forward cfg_access of
some registers to DM. For example: the opregion reg for GPU device.
This patch tried to add the support of emulated PCI ROM bar for the
device. And it doesn't handle the phys PCI ROM bar of phys PCI devices.
At the same time the rom firmware is provided in DM and pci rom bar_reg
is also emulated in DM, this leverages the quirk mechanism so that the
access to PCI rom bar_reg is forwarded to DM.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
Add the option of "romfile=file_location" to specify the rom file for rombar
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
The pci_reg 0x30 of PCI config_space is used to check whether the PCI rom
bar is supported. When the PCI rom is supported for the device in guest vm,
the 0x30 pci_reg is emulated and it can return the addr/enable bit.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
PCI ROM is the firmware specific to PCI device and it is provided by
the device vendor. The PCI rom resides in 0x30 offset of PCI config space.
This can be used to check whether the PCI rom exists. And when it exists,
it can load the firmware from the addr that is obtained from ROM bar addr.
For the user-vm, it will try to load the rom_file for the given PCI device and
enable the VM to access the firmware that is defined in rom_file.
BTW: The emulated rom_file is converted from efi image by using EfiRom. It has
no dependency on the ROM bar of physical PCI devices. Of course if the physical
PCI devices supports the ROM bar, the rom_file can also be dumped from the PCI
rom.
Now this is limited to PCI display device.
V2->V3: Add the function of pci_load_rombar/pci_release_rombar to handle the
rombar in course of passthrough_init/deinit.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
Now the device model only supports the 0..5 PCI bar for PCI/PCIE devices.
This tries to allocate the PCI_MEM32 resource for PCI ROM bar.
V1->V2: Use the PCI_ROMBAR as bar index and PCIBAR_ROM bar type when calling
the pci_emul_alloc_bar to allocate the guest physical addr for PCI ROM bar.
And it will allocate the resource from PCIBAR_MEM32 region.
V2->V3: Add more comments that describes the parameter of pci_emul_alloc_bar.
Tracked-On: #8175
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Wang Yu <yu1.wang@intel.com>
The application binary interface (ABI) is an important aspect of
hypercalls. But unfortunately it is not yet defined anywhere in the current
HLD.
This patch adds the current ABI specification to the hypercall section of
HLD.
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
With multiple xs:documentation nodes under the same xs:annotation, xs2js
will convert the XML into a dict where the key `xs:documentation` maps to a
list rather than a string. This patch enhances the converter.py to handle
such case properly.
Tracked-On: #8098
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Fix the bug in iothread handler, the event should be read out so that the
next epoll_wait not return directly as the fd can still readable.
Tracked-On: #8181
Signed-off-by: Conghui <conghui.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The design of ACRN CPU performance management is to let hardware
do the autonomous frequency selection(or set to a fixed value),
and remove guest's ability to control CPU frequency.
This patch is to remove guest's ability to control CPU frequency by
removing the guests' HWP/EIST CPUIDs and blocking the related MSR
accesses. Including:
- Remove CPUID.06H:EAX[7..11] (HWP)
- Remove CPUID.01H:ECX[7] (EIST)
- Inject #GP(0) upon accesses to MSR_IA32_PM_ENABLE,
MSR_IA32_HWP_CAPABILITIES, MSR_IA32_HWP_REQUEST,
MSR_IA32_HWP_STATUS, MSR_IA32_HWP_INTERRUPT,
MSR_IA32_HWP_REQUEST_PKG
- Emulate MSR_IA32_PERF_CTL. Value written to MSR_IA32_PERF_CTL
is just stored for reading. This is like how the native
environment would behavior when EIST is disabled from BIOS.
- Emulate MSR_IA32_PERF_STATUS by filling it with base frequency
state. This is consistent with Windows, which displays current
frequency as base frequency when running in VM.
- Hide the IA32_MISC_ENABLE bit 16 (EIST enable) from guests.
This bit is dependent to CPUID.01H:ECX[7] according to SDM.
- Remove CPID.06H:ECX[0] (hardware coordination feedback)
- Inject #GP(0) upon accesses to IA32_MPERF, IA32_APERF
Also DM do not need to generate _PSS/_PPC for post-launched VMs
anymore. This is done by letting hypercall HC_PM_GET_CPU_STATE sub
command ACRN_PMCMD_GET_PX_CNT and ACRN_PMCMD_GET_PX_DATA return (-1).
Tracked-On: #8168
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Reset the real_time_vcpu to 'n' if the VM is not a real-time VM.
Tracked-On: #8145
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
