3 Commits

Author	SHA1	Message	Date
Fei Li	0a13d0c7a4	uart16550: add a CONFIG to enable PCI uart16550 ... Now doesn't want introduce the PCI module since PCI CFG access should be arch special. Tracked-On: #8805 Signed-off-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-10-14 14:45:12 +08:00
Fei Li	83d56e0edb	vm: add necessary dummy APIs ... get_vm_from_vmid,is_paused_vm and is_poweroff_vm should be common APIs. But now doesn't implement them as common for not introduce more VM related data structure and APIs. Tracked-On: #8805 Signed-off-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-10-14 14:45:12 +08:00
Yifan Liu	1a2d5b9eed	hv: riscv: Add riscv build skeleton and hello world binary ... This commit adds riscv build skeleton and adds some dummy files that prints out hello world. To build riscv acrn.out/acrn.bin, simply: make hypervisor \ BOARD=<any existing board> \ SCENARIO=<any existing scenario> \ ARCH=riscv We still need to specify board and scenario as those were required by project level makefile. Tracked-On: #8782 Signed-off-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-03 14:41:33 +08:00