Commit Graph

9 Commits

Author SHA1 Message Date
Huihuang Shi
8b94957774 HV:guest:fix "signed/unsigned conversion without cast"
Misra C required signed/unsigned conversion with cast.

V1->V2:
  a.split patch to patch series

V2->V3:
  a.change the uint64_t type numeric constant's suffix from U to UL

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-04 12:18:38 +08:00
Junjie Mao
aa505a28bb HV: treewide: convert hexadecimals used in bitops to unsigned
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2018-06-21 13:12:39 +08:00
Huihuang Shi
fe0314e8c3 HV:header:fix "expression is not Boolean"
MISRA C explicit required expression should be boolean when
in branch statements (if,while...).

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-20 14:19:47 +08:00
Jason Chen CJ
48de7efa26 instr_emul: remove vm_restart_instruction and use VCPU_RETAIN_RIP
there is no need to use wrap function vm_restart_instruction, we
can use VCPU_RETAIN_RIP directly

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-06-11 12:14:43 +08:00
Huihuang Shi
e591315a65 HV:treewide:C99-friendly per_cpu implementation change the per_cpu method
The current implementation of per_cpu relies on several non-c99 features,
and in additional involves arbitrary pointer arithmetic which is not MIS-
RA C friendly.

This patch introduces struct per_cpu_region which holds all the per_cpu
variables. Allocation of per_cpu data regions and access to per_cpu vari-
ables are greatly simplified, at the cost of making all per_cpu varaibl-
es accessible in files.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
2018-06-05 17:09:00 +08:00
huihuang.shi
ba1b034e1e fix MISRA-C 243S
Included file not protected with #define, this
feature is required.

Signed-off-by: huihuang.shi <huihuang.shi@intel.com>
2018-05-31 11:26:13 +08:00
Binbin Wu
744e09bc7e hv: define 4 vcpu modes
move enum vm_cpu_mode to guest.h
move enum vm_paging_mode to guest.h
replace REAL_MODE with CPU_MODE_REAL
replace PAGE_PROTECTED_MODE with CPU_MODE_64BIT

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-24 10:16:48 +08:00
Yin Fengwei
4073b37369 hv: microcode: Enable microcode update from SOS.
microcode update from UOS is disabled.
microcode version checking is available for both SOS and UOS.

There are two TODOs of this patch:
1. This patch only update the uCode on pCPUs SOS owned. For the
   pCPUs not owned by SOS, the uCode is not updated. To handle
   this gap, we will have SOS own all pCPUs at boot time. So
   all pCPUs could have uCode updated. This will be handled
   in the patch to enable SOS own all pCPUs at boot time.

2. gva2gpa now doesn't check possible page table walk failure.
   Will add the failure check in gva2gpa in different patch.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Anthony Xu (anthony.xu@intel.com)
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-15 17:19:37 +08:00
Eddie Dong
7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00