7 Commits

Author	SHA1	Message	Date
Yonghua Huang	d6904b412c	hv: rename VM exit handlers in vlapic ... to keep aligned with the vmexit reasons' name defined in SPEC. Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>	2018-05-15 17:19:37 +08:00
Yonghua Huang	7d8803f5ea	hv:enable APICv features based on CPU capability ... this patch is to detect and enable only APICv features which are actually supported by the processor, instead fo tuning on all features by default. Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>	2018-05-15 17:19:37 +08:00
Yonghua Huang	f01a8eef58	Add APIC ACCESS VMexit handler ... Update 'apic_access_exit_handler()' function to emulate guest instruments to read/write guest's lapic registers page Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>	2018-05-15 17:19:37 +08:00
Yonghua Huang	9b269aee79	Add handle EOI case when APIC-write VM exit ... -If "virtual-interrupt delivery" VM-execution control is 0, Processor will causes an APIC-write VM exit if page offset is 0xB0 (EOI), SDM Vol3, Chapter 29.4.3 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>	2018-05-15 17:19:37 +08:00
Jason Chen CJ	fcb95d02d6	uefi: init vlapic according to native lapic ... this patch save native lapic configuration and restore it to vm0's vlapic before its running, then doing hpet timer interrupt injection through vlapic interface -- this will not mess up vlapic and we can see hpet timer interrupt coming continuously. Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>	2018-05-15 17:19:37 +08:00
Yonghua Huang	83e78e16c7	align the coding style when access VMEXIT_QUAL ... - align coding style to avoid redundant operations when operating on reading VMX_EXIT_QUALIFICATION Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>	2018-05-15 17:19:36 +08:00
Eddie Dong	7a3a539b17	initial import ... internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>	2018-05-11 14:44:28 +08:00