3 Commits

Author	SHA1	Message	Date
Chenli Wei	a1b266f807	misc: refine CLOS module for expansibility ... This patch refine CLOS module by the following aspects: 1 Unified CACHE_ID type to Hex Format 2 Rewrite policy merge with RDT Class 3 Modify the logic of generate CPU mask Signed-off-by: Chenli Wei <chenli.wei@intel.com>	2022-05-11 17:00:51 +08:00
Chenli Wei	3b4841b91d	misc: fix the issue of create hv node ... There was an issue of create hv node by clos module, the direct cause is the create logic and the indirect cause is these modules of static_allocators was not sorted before run which cause some platform have issue and CI could not found. So this patch fix the create issue and sorted the modules list to make sure all these platform could work well and get the same allocation.xml Tracked-On: #6690 Signed-off-by: Chenli Wei <chenli.wei@intel.com>	2022-04-28 13:42:54 +08:00
Chenli Wei	4807385fe2	misc: refine cache config ... The current RDT setting requires users to calculate the CLOS mask and the details, it is not a user-friendly setting. So we redesigned RDT, users can easily specify the cache of each vcpu for VMs. This patch add an RDT region element for schema, calculate and generate all the mask and rdt parameters by config tool to generates rdt_info struct for board.c. Tracked-On: #6690 Signed-off-by: Chenli Wei <chenli.wei@intel.com>	2022-04-24 16:52:24 +08:00