This patch checks the obsoleted parameters and print some warnings
instead of exiting the acrn-dm directly. The following obsoleted
parameters are covered:
-i, --ioc_node
-G, --gvtargs
-Y, --mptgen
--vsbl
--part_info
--pm_by_vuart
--pm_notify_channel
Tracked-On: #6690
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
1.Unified the function naming style in this file
2.Added the procedure for possible input 0 value of hpa_region in check_hpa()
3.Modified the delimiting spaces between two lines
Tracked-On: #6690
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Ziheng L1 <ziheng.li@intel.com>
1. After the data structure of vm/memory in scenario and schema files.
The scenario will look like this.
<hpa_region>
<start_hpa>xxx</start_hpa>
<size_hpa>xxx</size_hpa>
</hpa_region>
We should change all XMLs for the new design.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
1. Update the data structure of vm/memory in scenario and schema files.
The scenario will look like this.
<hpa_region>
<start_hpa>xxx</start_hpa>
<size_hpa>xxx</size_hpa>
</hpa_region>
2. Update xsl files to generate the related struct.
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
The current code only supports 2 HPA regions per VM.
This patch extended ACRN to support 2+ HPA regions per VM, to use host
memory better if it is scatted among multiple regions.
This patch uses an array to describe the hpa region for the VM, and
change the logic of ve820 to support multiple regions.
This patch dependent on the config tool and GPA SSRAM change
Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
The cpu_id is allocated contiguously by the kernel, start at 0.
However, today's cache information extractors parse them as hexadecimal number,
more than 10 will result in incomplete cache information.
The issue now is fixed, so update the board xml.
Tracked-On: #6689
Signed-off-by: zhongzhenx.liu <zhongzhenx.liu@intel.com>
Virtio gpu device UI will be implemented after 3.0.
As a workaround, this patch simply adds the virtio gpu entry in schema
and launch script generation logic.
Tracked-On: #7301
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Otherwise it will use the "acrn_dm" as the thread_name, which is not
convenient to check the cpu_usage of rendering_thread.
Tracked-On: #7337
Acked-by: Wang Yu <yu1.wang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
In course of creating the udmabuf, udmabuf_create_list is allocated and
passed to kernel. After the dmabuf is returned, it is not used
any more. Need to free it otherwises it will cause the memory leak.
Tracked-On: #7337
Acked-by: Wang Yu <yu1.wang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
It still tries to access the gpu->vdpy_handel after the gpu
is free. This is incorrect.
Tracked-On: #7337
Acked-by: Wang Yu <yu1.wang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
When virtio-gpu tries to submit the framebuffer based on
VIRTIO_GPU_CMD_2D, one pixman_image will be created. When the
sdl rendering_thread is terminated, the pixman_image will be
released. But its pointer is set to NULL. In the next reboot,
its access in vdpy_surface_set is incorrect.
Tracked-On: #7337
Acked-by: Wang Yu <yu1.wang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Unlike other CPU IDs, the cpu_id field under //processors//thread in the
board XML is in decimal as it is assigned by the kernel continuously,
starting from 0. However, the cache info extractor today parses them as
hexadecimal numbers, leading to incomplete cache info when more than 10
processors are present on the board. This patch fixes this issue.
Tracked-On: #6689
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Today ACRN works only on platforms with a single PCI domain (which is true
for most client and IoT platforms). This limitation is also used to
simplify the implementation of the board inspector. As a result, on
platforms with multiple PCI domains, the board inspector may crash when
parsing information about PCI devices.
This patch adds a check on the number of PCI domains before the board
inspector attempts to extract any information, and terminates the tool
early if multiple PCI domains are detected.
Tracked-On: #6689
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch adds the import of the `sys` module in platformbase.py which
uses `sys.exit` to terminate the board inspector upon fatal errors.
Tracked-On: #6689
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The lookup extractor of the board inspector filters out non-PCI or
non-present devices by checking the presence of vendor ID and class code.
The same logic applies to PCI buses as well, but is neglected today.
This patch adds the missing check.
Tracked-On: #6689
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
According to DX recommendations, this patch adds a Boolean item to each
vCPU which allows users to specify the vCPUs intended for
real-time-critical tasks. This information will be used to organize other
widgets (CAT-related ones for now) in the configurator to tell apart
real-time ones from the others for better clarity.
All vCPUs are by default not real-time-critical, except those in the RT VMs
which are.
Tracked-On: #6690
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch adds the command line option --add-llc-cat to the board
inspector to allow users adding CAT capabilities of the last level cache to
the generated board XML even when the hardware does not report so for any
reason.
Tracked-On: #6690
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch adds the assertion (in XSD) that validates if all explicitly
specified vBDF (including those for virtual UART controllers and IVSHMEM
interfaces) are unique.
Tracked-On: #7330
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Different from other nodes which have static default values, the virtual
BDF nodes of virtual UART endpoints or IVSHMEM interfaces have a set of
default values and should be used with uniqueness guaranteed. The existing
default value mechanism in XSD does not include support for this.
This patch adds two more ACRN-specific annotations, namely `acrn:defaults`
and `acrn:unique-among`, that have the following semantics.
- `acrn:defaults` is a Python expression that evaluates to an iterable.
- `acrn:unique-among` is an xpath that specifies the nodes. Each node
within the select ones shall have a value unique among them. The xpath
is evaluated with the variable `parent` defined as the parent node
under which the vBDF node is to be appended.
Tracked-On: #7330
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
When CPUID executes with EAX set to 1AH, the processor returns information about hybrid capabilities.
This information is percpu related, and should be obtained directly from the physical cpu.
Tracked-On: #6899
Signed-off-by: Tw <wei.tan@intel.com>
Add documentation for enumerated types and value restrictions so it
shows up in the option documention. Also add additional acrn:title
annotations.
Tracked-On: #5692
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Documentation continuation lines must not be indented unless required by
rst syntax.
Added some type explations for enumerations, but would be better to
generate the enumeration values by scanning the tree. Figure that out in
another PR. (This would prevent the documented list of values from
being out of sync with the actual list of values in the enumeration.)
Tracked-On: #5692
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Page table entry present check is page table type
specific and static, e.g. just need to check bit0
of page entry for entries of MMU page table and
bit2~bit0 for EPT page table case. hence no need to
check it by callback function every time.
This patch remove 'pgentry_present' callback field and
add a new bitmask field for this page entry present check.
It can get better performance especially when this
check is executed frequently.
Tracked-On: #7327
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
When CPUID executes with EAX set to 02H, the processor returns information about cache and TLB information.
This information is percpu related, and should be obtained directly from the physical cpu.
BTW, this patch is backported from v2.7 branch.
Tracked-On: #6931
Signed-off-by: Tw <wei.tan@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
This patch is to eliminate a code scan warning.
p_elf_header32 was given a value when it was declared, but later it was
given the same value again. Just remove the later one.
Tracked-On: #7318
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Because Board Inspector modifies the SR-IOV function,
VF information is correctly captured when Board Inspector
collects Board information. So update the board xmls
Tracked-On: #7031
Signed-off-by: zhongzhenx.liu <zhongzhenx.liu@intel.com>
Now all the 3D ops are handled in one dedicated thread. As 3D ops are
not safe in multi-thread env, some checks are added so that it can indicate
that it is not in the expected code path.
Tracked-On: #7296
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Otherwise the memory related with vga_context is leaked.
v1->v2: Use the pthread_join instead of usleep to wait for
the termination of vga_thread.
Tracked-On: #7296
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
This is not needed as it is reconfigured in course of vga_thread_loop.
At the same time it is not thread-safe as the 3D api is involved
in vdpy_surface_set.
v2->v3: move the initialization of vga_surface width/height into
vga_thread.
Tracked-On: #7296
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
In order to support the VGA op, one vga_thread is created. But
in course of virtio_gpu_reset, it will also create one vga_thread.
This is incorrect.
v1->v2: the thread_id of vga_thread is treated as read-only after
the thread is created.
One thread_status based on atomic type indicates the life_cycle
of vga_thread.
v2->v3: Add the vga_thread_mtx in course of changing life_cycle of vga_thread
Tracked-On: #7296
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Now interrupt vector in ACRN hypervisor is maintained as global variable, not
per-CPU variable. If there're more PCI devices, the physical interrupt vectors
are not enough most likely.
This patch would not allocate physical interrupt vector for MSI/MSI-X vectors
if interrupt posting could been used to inject the MSI/MSI-X interrupt to
a VM directly.
Tracked-On: #7275
Signed-off-by: Fei Li <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Bugfix:bootargs is optional parameter, which may be not
present in xml as a node, asl_gen.py needs to process
that case.
Tracked-On: #7307
Signed-off-by: hangliu1 <hang1.liu@linux.intel.com>
The read-the-docs theme uses a reduced font size within tables. The CSS
used though is overly restrictive and doesn't properly handle tables
containing lists or other constructs where the paragraph tags don't have
the <td> tag within the table as the immediate parent. Add an
overriding style in our custom CSS to fix this so the font size on lists
within a table are the same as normal paragraphs within a table.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Using the SSRAM area size extracted by config_tools, the patch changes
the hard-coded GPA SSRAM area size to its actual size, so that
pre-launched VMs can support large(>8MB) SSRAM area.
When booting service VM, the SSRAM area has to be removed from Service
VM's mem space, because they are passed-through to the pre-rt VM. The
code was bugged since it was using the SSRAM area's GPA in the pre-rt
VM. Changed it to GPA in Service VM.
Tracked-On: #7212
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
The GPA SSRAM area size in pre-launched VMs was hard-coded to 8MB.
Since this area is mapped from host SSRAM area, it will cause compile
problem when host's SSRAM area is larger than 8MB.
To solve this issue, we have to calculate SSRAM area's size in
gpa.py, and generate a macro PRE_RTVM_SW_SRAM_MAX_SIZE for HV
to use.
PRE_RTVM_SW_SRAM_START_GPA/END_GPA can be calculated by end/size
in HV, so they are removed.
When SSRAM is not configured in the system, PRE_RTVM_SW_SRAM_MAX_SIZE
is set to 0.
Crl_bin is not needed in guest. So it's size is removed in bin_gen.py.
Tracked-On: #7212
Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
On hybrid platform(e.g. ADL), there may be multiple instances of same level caches for different type of processors,
The current design only supports one global `rdt_info` for each RDT resource type.
In order to support hybrid platform, this patch introduce `rdt_ins` to represents the "instance".
Also, the number of `rdt_info` is dynamically generated by config-tool to match with physical board.
Tracked-On: projectacrn#6690
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
