3 Commits

Author	SHA1	Message	Date
Fei Li	f687574a58	vuart: add dummy vuart for risc-v ... vUART will not enable before VM could be created. Tracked-On: #8805 Signed-off-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-10-14 14:45:12 +08:00
Xue Bosheng	6de0e4b681	hv: add dummy function for riscv support ... add dummy function "need_offline", "need_shutdown_vm", "shutdown_vm_from_idle" to support riscv. Tracked-On: #8812 Signed-off-by: Xue Bosheng <bosheng.xue@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-30 12:31:07 +08:00
hangliu1	286c383b53	hv: multiarch: riscv: add dummy header for riscv ... add dummy headrer file for early compile, should be replaced totally later. Tracked-On: #8801 Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Wang, Yu1 <yu1.wang@intel.com> Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-19 15:04:55 +08:00