3 Commits

Author	SHA1	Message	Date
Jiaqing Zhao	5803232d83	hv: enable acrnlog in release builds ... Enable acrnlog (memory logging) in release builds, default log level is still controlled by DEBUG_OPTIONS/MEM_LOGLEVEL in scenario file. Tracked-On: #8805 Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com>	2025-09-25 16:30:26 +08:00
Jian Jun Chen	17c9a4d7be	hv: riscv: implement basic logic to bring up APs ... This patch adds the basic logics to bring up all APs in the C entry of BSP boot. The mapping between logcial CPU IDs and physical hart IDs is setup based on the pre-generated data from config tool by parsing the device tree. Logical CPU ID BSP_CPU_ID will always map to the BSP hart ID. The per pCPU logic ID is saved in tp register. Tracked-On: #8791 Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-23 11:30:38 +08:00
Jian Jun Chen	b854a24109	hv: risc-v: add C entry function of BSP and APs ... Tracked-On: #8788 Signed-off-by: Haicheng Li <haicheng.li@intel.com> Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-15 13:12:21 +08:00