BIOS Information Vendor: Intel Corp. Version: AYAPLCEL.86A.0063.2019.0621.1450 Release Date: 06/21/2019 BIOS Revision: 5.6 Base Board Information Manufacturer: Intel Corporation Product Name: NUC6CAYB Version: J23203-404 00:00.0 Host bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Host Bridge (rev 0b) 00:02.0 VGA compatible controller: Intel Corporation Device 5a85 (rev 0b) Region 0: Memory at 90000000 (64-bit, non-prefetchable) [size=16M] Region 2: Memory at 80000000 (64-bit, prefetchable) [size=256M] 00:0e.0 Audio device: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Audio Cluster (rev 0b) Region 0: Memory at 91410000 (64-bit, non-prefetchable) [size=16K] Region 4: Memory at 91000000 (64-bit, non-prefetchable) [size=1M] 00:0f.0 Communication controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Trusted Execution Engine (rev 0b) Region 0: Memory at 91427000 (64-bit, non-prefetchable) [size=4K] 00:12.0 SATA controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SATA AHCI Controller (rev 0b) Region 0: Memory at 91414000 (32-bit, non-prefetchable) [size=8K] Region 1: Memory at 91424000 (32-bit, non-prefetchable) [size=256] Region 5: Memory at 91423000 (32-bit, non-prefetchable) [size=2K] 00:13.0 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port A #1 (rev fb) 00:13.1 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port A #2 (rev fb) 00:13.2 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port A #3 (rev fb) 00:15.0 USB controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series USB xHCI (rev 0b) Region 0: Memory at 91400000 (64-bit, non-prefetchable) [size=64K] 00:16.0 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #1 (rev 0b) Region 0: Memory at 91422000 (64-bit, non-prefetchable) [size=4K] Region 2: Memory at 91421000 (64-bit, non-prefetchable) [size=4K] 00:18.0 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series HSUART Controller #1 (rev 0b) Region 0: Memory at 91420000 (64-bit, non-prefetchable) [size=4K] Region 2: Memory at 9141f000 (64-bit, non-prefetchable) [size=4K] 00:19.0 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SPI Controller #1 (rev 0b) Region 0: Memory at 9141e000 (64-bit, non-prefetchable) [size=4K] Region 2: Memory at 9141d000 (64-bit, non-prefetchable) [size=4K] 00:19.1 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SPI Controller #2 (rev 0b) Region 0: Memory at 9141c000 (64-bit, non-prefetchable) [size=4K] Region 2: Memory at 9141b000 (64-bit, non-prefetchable) [size=4K] 00:19.2 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SPI Controller #3 (rev 0b) Region 0: Memory at 9141a000 (64-bit, non-prefetchable) [size=4K] Region 2: Memory at 91419000 (64-bit, non-prefetchable) [size=4K] 00:1a.0 Serial bus controller [0c80]: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PWM Pin Controller (rev 0b) Region 0: Memory at 91418000 (64-bit, non-prefetchable) [size=4K] Region 2: Memory at 91417000 (64-bit, non-prefetchable) [size=4K] 00:1f.0 ISA bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Low Pin Count Interface (rev 0b) 00:1f.1 SMBus: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SMBus Controller (rev 0b) Region 0: Memory at 91416000 (64-bit, non-prefetchable) [size=256] 01:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. RTS5229 PCI Express Card Reader (rev 01) Region 0: Memory at 91300000 (32-bit, non-prefetchable) [size=4K] 02:00.0 Network controller: Intel Corporation Device 24fb (rev 10) Region 0: Memory at 91200000 (64-bit, non-prefetchable) [size=8K] 03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15) Region 2: Memory at 91104000 (64-bit, non-prefetchable) [size=4K] Region 4: Memory at 91100000 (64-bit, non-prefetchable) [size=16K] 00:00.0 0600: 8086:5af0 (rev 0b) 00:02.0 0300: 8086:5a85 (rev 0b) 00:0e.0 0403: 8086:5a98 (rev 0b) 00:0f.0 0780: 8086:5a9a (rev 0b) 00:12.0 0106: 8086:5ae3 (rev 0b) 00:13.0 0604: 8086:5ad8 (rev fb) 00:13.1 0604: 8086:5ad9 (rev fb) 00:13.2 0604: 8086:5ada (rev fb) 00:15.0 0c03: 8086:5aa8 (rev 0b) 00:16.0 1180: 8086:5aac (rev 0b) 00:18.0 1180: 8086:5abc (rev 0b) 00:19.0 1180: 8086:5ac2 (rev 0b) 00:19.1 1180: 8086:5ac4 (rev 0b) 00:19.2 1180: 8086:5ac6 (rev 0b) 00:1a.0 0c80: 8086:5ac8 (rev 0b) 00:1f.0 0601: 8086:5ae8 (rev 0b) 00:1f.1 0c05: 8086:5ad4 (rev 0b) 01:00.0 ff00: 10ec:5229 (rev 01) 02:00.0 0280: 8086:24fb (rev 10) 03:00.0 0200: 10ec:8168 (rev 15) #define WAKE_VECTOR_32 0x7962108CUL #define WAKE_VECTOR_64 0x79621098UL #define RESET_REGISTER_ADDRESS 0xCF9UL #define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO #define RESET_REGISTER_VALUE 0x6U #define PM1A_EVT_SPACE_ID SPACE_SYSTEM_IO #define PM1A_EVT_BIT_WIDTH 0x20U #define PM1A_EVT_BIT_OFFSET 0x0U #define PM1A_EVT_ADDRESS 0x400UL #define PM1A_EVT_ACCESS_SIZE 0x2U #define PM1B_EVT_SPACE_ID SPACE_SYSTEM_IO #define PM1B_EVT_BIT_WIDTH 0x0U #define PM1B_EVT_BIT_OFFSET 0x0U #define PM1B_EVT_ADDRESS 0x0UL #define PM1B_EVT_ACCESS_SIZE 0x2U #define PM1A_CNT_SPACE_ID SPACE_SYSTEM_IO #define PM1A_CNT_BIT_WIDTH 0x10U #define PM1A_CNT_BIT_OFFSET 0x0U #define PM1A_CNT_ADDRESS 0x404UL #define PM1A_CNT_ACCESS_SIZE 0x2U #define PM1B_CNT_SPACE_ID SPACE_SYSTEM_IO #define PM1B_CNT_BIT_WIDTH 0x0U #define PM1B_CNT_BIT_OFFSET 0x0U #define PM1B_CNT_ADDRESS 0x0UL #define PM1B_CNT_ACCESS_SIZE 0x2U #define S3_PKG_VAL_PM1A 0x5U #define S3_PKG_VAL_PM1B 0U #define S3_PKG_RESERVED 0x0U #define S5_PKG_VAL_PM1A 0x7U #define S5_PKG_VAL_PM1B 0U #define S5_PKG_RESERVED 0x0U #define DRHD_COUNT 2U #define DRHD0_DEV_CNT 1U #define DRHD0_SEGMENT 0U #define DRHD0_FLAGS 0U #define DRHD0_REG_BASE 0xFED64000UL #define DRHD0_IGNORE false #define DRHD0_DEVSCOPE0_BUS 0x0U #define DRHD0_DEVSCOPE0_PATH 0x10U #define DRHD0_DEVSCOPE1_BUS 0x0U #define DRHD0_DEVSCOPE1_PATH 0x0U #define DRHD0_DEVSCOPE2_BUS 0x0U #define DRHD0_DEVSCOPE2_PATH 0x0U #define DRHD0_DEVSCOPE3_BUS 0x0U #define DRHD0_DEVSCOPE3_PATH 0x0U #define DRHD1_DEV_CNT 2U #define DRHD1_SEGMENT 0U #define DRHD1_FLAGS 1U #define DRHD1_REG_BASE 0xFED65000UL #define DRHD1_IGNORE false #define DRHD1_DEVSCOPE0_BUS 0xfaU #define DRHD1_DEVSCOPE0_PATH 0xf8U #define DRHD1_DEVSCOPE1_BUS 0x0U #define DRHD1_DEVSCOPE1_PATH 0xffU #define DRHD1_DEVSCOPE2_BUS 0x0U #define DRHD1_DEVSCOPE2_PATH 0x0U #define DRHD1_DEVSCOPE3_BUS 0x0U #define DRHD1_DEVSCOPE3_PATH 0x0U #define DRHD1_IOAPIC_ID 1U #define DRHD2_DEV_CNT 0U #define DRHD2_SEGMENT 0U #define DRHD2_FLAGS 0U #define DRHD2_REG_BASE 0x00UL #define DRHD2_IGNORE false #define DRHD2_DEVSCOPE0_BUS 0x0U #define DRHD2_DEVSCOPE0_PATH 0x0U #define DRHD2_DEVSCOPE1_BUS 0x0U #define DRHD2_DEVSCOPE1_PATH 0x0U #define DRHD2_DEVSCOPE2_BUS 0x0U #define DRHD2_DEVSCOPE2_PATH 0x0U #define DRHD2_DEVSCOPE3_BUS 0x0U #define DRHD2_DEVSCOPE3_PATH 0x0U #define DRHD3_DEV_CNT 0U #define DRHD3_SEGMENT 0U #define DRHD3_FLAGS 0U #define DRHD3_REG_BASE 0x00UL #define DRHD3_IGNORE false #define DRHD3_DEVSCOPE0_BUS 0x0U #define DRHD3_DEVSCOPE0_PATH 0x0U #define DRHD3_DEVSCOPE1_BUS 0x0U #define DRHD3_DEVSCOPE1_PATH 0x0U #define DRHD3_DEVSCOPE2_BUS 0x0U #define DRHD3_DEVSCOPE2_PATH 0x0U #define DRHD3_DEVSCOPE3_BUS 0x0U #define DRHD3_DEVSCOPE3_PATH 0x0U "Intel(R) Celeron(R) CPU J3455 @ 1.50GHz" {{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */ {{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x415UL}, 0x02U, 0x32U, 0x00U}, /* C2 */ {{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x419UL}, 0x03U, 0x96U, 0x00U}, /* C3 */ {0x5DDUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001700UL, 0x001700UL}, /* P0 */ {0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P1 */ {0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P2 */ {0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P3 */ {0x4B0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000C00UL, 0x000C00UL}, /* P4 */ {0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P5 */ {0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P6 */ {0x384UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000900UL, 0x000900UL}, /* P7 */ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P8 */ clos supported by cache:L2 clos max:4 00001000-0003efff : System RAM 00040000-0009efff : System RAM 00100000-0fffffff : System RAM 12151000-6ff60017 : System RAM 6ff60018-6ff6e057 : System RAM 6ff6e058-6ff6f017 : System RAM 6ff6f018-6ff7f057 : System RAM 6ff7f058-7710dfff : System RAM 799f6000-79d78fff : System RAM 79da4000-7a9defff : System RAM 7a9e1000-7affffff : System RAM 100000000-27fffffff : System RAM /dev/sda3: LABEL="root" UUID="b8352fb7-25f5-481d-aa6f-015a7c76c5aa" TYPE="ext4" PARTLABEL="/" PARTUUID="9a305316-3c78-436c-9c21-3be1b324428d" BDF:(00:18.0) seri:/dev/ttyS0 base:0x91420000 irq:4 3, 5, 6, 7, 10, 11, 12, 13, 15 8062792 kB 0, 1, 2, 3