Options for debugging the hypervisor. Identify build type. Debug mode enables debug shell, prints, and logs. Release mode optimizes the ACRN binary for deployment and turns off all debug infrastructure. These can only be changed at build time. Specify the host serial device used for hypervisor debugging. Specify default log level for log messages stored in memory. Value can be changed at runtime. Log messages with the selected value or lower are displayed. Specify default log level for the hypervisor via Intel Trace Hub log. Use the Intel Trace Hub's memory to record log messages. Value can be changed at runtime. Log messages with the selected value or lower are displayed. Specify default log level for log messages written to the serial console. Log messages with the selected value or lower are displayed. Options for enabling hypervisor features. Enable hypervisor relocation in memory. The boot loader may need to change the location of the hypervisor because of other firmware. Choose scheduling algorithm used for determining which User VM runs on a shared virtual CPU. Enable multiboot2 boot protocol support and multiboot1 downward compatibility. Disable this feature if multiboot1 meets your requirements and to reduce lines of code. Enable split lock detection for real-time application. This prevents alignment check exceptions from impacting hypervisor real-time performance. Enable UC lock detection for real-time application. This prevents general protection faults from impacting hypervisor real-time performance. Enable to do fixup for TPM2 and SMBIOS for Security VM. If no Security VM, setting this option to ``n`` If ``y``, permanently disables all interrupts in HV root mode. Enable Intel Resource Director Technology (RDT). The technology provides cache and memory allocation features to improve time performance of real-time VMs. Enable Microsoft(R) Hypervisor Top-Level Functional Specification for Windows hyper-v support. Specify if the IOMMU enforces snoop behavior of DMA operations. Enable ACPI runtime parsing to get DMAR (DMA remapping) configuration data from the APCI tables. Otherwise, use existing, static information from the associated board.xml file. Enable L1 cache flush before VM entry,Determine the enabling of mitigation solution for L1 Terminal Fault (L1TF). The L1 data cache will be flushed before each VMENTRY.L1TF is a speculative execution side channel cache timing vulnerability. Each variety of L1TF could potentially allow unauthorized disclosure of information residing in the L1 data cache. Enable software workaround for Machine Check Error on Page Size Change (silicon bug in some processor families). Capacity of one stack (in bytes) used by a physical core. Each core uses one stack for normal operation and another three for specific exceptions. The 2MB-aligned starting physical address of the RAM region used by the hypervisor. Capacity limits for static assigned data structure or maximum supported resource. Maximum number of User VMs allowed. Highest PCI bus ID used during IOMMU initialization. Maximum number of IOAPICs. Integer from 1 to 10. Specify the static memory allocation of maximum number of PCI devices. (Default value is 96) Integer from 1 to 1024. Maximum number of interrupt lines per IOAPIC. Integer from 1 to 120. The pre-defined number of interrupt sources of all pass-through devices. Specify maximum number of MSI-X tables per device. If this value is empty, then the default value will be calculated from the board XML file. (Default value is 64) Integer value from 1 to 2048. Specify maximum number of emulated MMIO regions. (Default value is 16) Integer value from 1 to 128. Segment, Bus, Device, and function of the GPU. Configure the debug facilities. Enable hypervisor features. Configure memory used by the hypervisor. Configure the capacities of the hypervisor. Miscellaneous options for workarounds. Specify the vUART connection setting. Refer to :ref:`vuart_config` for detailed vUART settings. Specify the load_order. Specify the VM type. Type in the name used to identify each VM. The VM name will be shown in the hypervisor console vm_list command. string from 1 to 32 characters long. Specify LAPIC to passthrough. Specify Polling mode for IO Completion. Specify nested virtualization support for KVM. Specify virtual CAT support for VM. Specify secure world support for trustry OS. Specify MTRR capability to hide for VM. Specify TPM2 FIXUP for VM. List of pCPU that this VM's vCPUs are pinned to. Class of Service for Cache Allocation Technology. Refer SDM 17.19.2 for details, and use with caution. Specify SGX Enclave Page Cache section base and size in byte. It must be page aligned. Specify memory information for Service and User VMs. Specify the VM vCPU priority for scheduling. Specify the companion VM id of this VM. General information for host kernel, boot argument and memory. Specify the console vUART (aka PCI based vUART) with the vUART ID by its ``id`` attribute. MMIO resources to passthrough. Determine the static memory size of pt_intx array. It is used to describe the pre-launched VM owned ioapic pins and the corresponding mapping between physical GSI and virtual GSI. Enable virtualization of PCIE Precision Time Measurement (PTM) mechanism for devices with PTM capability and for real-time application. HV provides PCIE root port emulation instead of host bridge emulation for VM , PTM could coordinate timing between device and root port with device’s local timebases without relying on software. The hypervisor configuration defines a working scenario and target board by configuring the hypervisor image features and capabilities such as setting up the log and the serial port. VM configuration includes **scenario-based** VM configuration information that is used to describe the characteristics and attributes for all VMs in a user scenario. It also includes **launch script-based** VM configuration information, where parameters are passed to the device model to launch post-launched User VMs.