mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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86e37fbe01
Add configurations code of industry scenario and hybrid_rt scenario for cfl-k700-i7 board to support build acrn binary from source code directly. Tracked-On: #5212 Signed-off-by: Victor Sun <victor.sun@intel.com>
96 lines
3.9 KiB
C
96 lines
3.9 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: INSYDE Corp.
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* Version: Z01-0001A027
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* Release Date: 10/14/2019
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* BIOS Revision: 1.28
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*
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* Base Board Information
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* Manufacturer: Logic Supply
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* Product Name: RXM-181
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* Version: Type2 - Board Version
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*/
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#ifndef PCI_DEVICES_H_
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#define PCI_DEVICES_H_
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#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}
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#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}
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#define SYSTEM_PERIPHERAL_0 .pbdf.bits = {.b = 0x00U, .d = 0x08U, .f = 0x00U}
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#define SIGNAL_PROCESSING_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x00U}
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#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
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#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}
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#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x01U}
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#define SERIAL_BUS_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U}
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#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}
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#define COMMUNICATION_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x00U}
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#define SERIAL_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x03U}
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#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}
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#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x00U}
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#define PCI_BRIDGE_1 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x06U}
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#define PCI_BRIDGE_2 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U}
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#define PCI_BRIDGE_3 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x06U}
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#define PCI_BRIDGE_4 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x07U}
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#define PCI_BRIDGE_5 .pbdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x00U}
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#define PCI_BRIDGE_6 .pbdf.bits = {.b = 0x03U, .d = 0x01U, .f = 0x00U}
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#define PCI_BRIDGE_7 .pbdf.bits = {.b = 0x03U, .d = 0x02U, .f = 0x00U}
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#define PCI_BRIDGE_8 .pbdf.bits = {.b = 0x03U, .d = 0x03U, .f = 0x00U}
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#define PCI_BRIDGE_9 .pbdf.bits = {.b = 0x03U, .d = 0x04U, .f = 0x00U}
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#define PCI_BRIDGE_10 .pbdf.bits = {.b = 0x03U, .d = 0x05U, .f = 0x00U}
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#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U}
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#define AUDIO_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U}
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#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U}
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#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x06U}
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#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x04U, .d = 0x00U, .f = 0x00U}
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#define ETHERNET_CONTROLLER_2 .pbdf.bits = {.b = 0x05U, .d = 0x00U, .f = 0x00U}
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#define ETHERNET_CONTROLLER_3 .pbdf.bits = {.b = 0x06U, .d = 0x00U, .f = 0x00U}
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#define ETHERNET_CONTROLLER_4 .pbdf.bits = {.b = 0x07U, .d = 0x00U, .f = 0x00U}
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#define ETHERNET_CONTROLLER_5 .pbdf.bits = {.b = 0x0AU, .d = 0x00U, .f = 0x00U}
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#define ETHERNET_CONTROLLER_6 .pbdf.bits = {.b = 0x0BU, .d = 0x00U, .f = 0x00U}
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#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U}
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#define NON_VOLATILE_MEMORY_CONTROLLER_1 .pbdf.bits = {.b = 0x09U, .d = 0x00U, .f = 0x00U}
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#endif /* PCI_DEVICES_H_ */
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