mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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e8b25bbbdb
so that vm_configurations.h/vm_configurations.c are consistent for same scenario Upload configuration source code for: Board scenarios whl-ipc-i5 industry, hybrid, hybrid_rt, logical_partiton whl-ipc-i7 industry, hybrid, hybrid_rt, logical_partiton ehl-crb-b industry, hybrid, hybrid_rt, logical_partition nuc7i7dnb industry, hybrid, logical_partition Tracked-On: #5229 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
93 lines
3.8 KiB
C
93 lines
3.8 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: Intel Corporation
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* Version: EHLSFWI1.R00.2224.A00.2005281500
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* Release Date: 05/28/2020
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*
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* Base Board Information
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* Manufacturer: Intel Corporation
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* Product Name: ElkhartLake LPDDR4x T3 CRB
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* Version: 2
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*/
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#ifndef PCI_DEVICES_H_
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#define PCI_DEVICES_H_
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#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}
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#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}
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#define SYSTEM_PERIPHERAL_0 .pbdf.bits = {.b = 0x00U, .d = 0x08U, .f = 0x00U}
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#define SYSTEM_PERIPHERAL_1 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x10U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x10U, .f = 0x01U}
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#define SERIAL_BUS_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_3 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_4 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x02U}
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#define SERIAL_BUS_CONTROLLER_5 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x03U}
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#define SERIAL_BUS_CONTROLLER_6 .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_7 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x00U}
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#define SERIAL_BUS_CONTROLLER_8 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x01U}
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#define SERIAL_BUS_CONTROLLER_9 .pbdf.bits = {.b = 0x00U, .d = 0x1BU, .f = 0x06U}
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#define SERIAL_BUS_CONTROLLER_10 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U}
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#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x04U}
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#define COMMUNICATION_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x13U, .f = 0x05U}
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#define COMMUNICATION_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}
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#define COMMUNICATION_CONTROLLER_3 .pbdf.bits = {.b = 0x00U, .d = 0x19U, .f = 0x02U}
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#define COMMUNICATION_CONTROLLER_4 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x00U}
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#define COMMUNICATION_CONTROLLER_5 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x01U}
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#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
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#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}
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#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}
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#define SD_HOST_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x00U}
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#define SD_HOST_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x01U}
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#define NON_VGA_UNCLASSIFIED_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x03U}
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#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U}
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#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x01U}
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#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x02U}
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#define ETHERNET_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x1EU, .f = 0x04U}
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#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U}
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#define MULTIMEDIA_AUDIO_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U}
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#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U}
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#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U}
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#endif /* PCI_DEVICES_H_ */
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