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https://github.com/projectacrn/acrn-hypervisor.git
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29ac258134
1.Modify clos_mask and mba_delay as a member of the union type. 2.Move HV_SUPPORTED_MAX_CLOS ,MAX_CACHE_CLOS_NUM_ENTRIES and MAX_MBA_CLOS_NUM_ENTRIES to misc_cfg.h file. Tracked-On: #5229 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
107 lines
3.1 KiB
C
107 lines
3.1 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: American Megatrends Inc.
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* Version: WL10R104
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* Release Date: 09/12/2019
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* BIOS Revision: 5.13
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*
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* Base Board Information
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* Manufacturer: Maxtang
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* Product Name: WL10
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* Version: V1.0
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*/
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#include <board.h>
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#include <vtd.h>
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#include <msr.h>
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#include <pci.h>
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#include <misc_cfg.h>
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static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
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{
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.type = DRHD0_DEVSCOPE0_TYPE,
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.id = DRHD0_DEVSCOPE0_ID,
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.bus = DRHD0_DEVSCOPE0_BUS,
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.devfun = DRHD0_DEVSCOPE0_PATH,
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},
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};
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static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = {
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{
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.type = DRHD1_DEVSCOPE0_TYPE,
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.id = DRHD1_DEVSCOPE0_ID,
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.bus = DRHD1_DEVSCOPE0_BUS,
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.devfun = DRHD1_DEVSCOPE0_PATH,
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},
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{
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.type = DRHD1_DEVSCOPE1_TYPE,
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.id = DRHD1_DEVSCOPE1_ID,
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.bus = DRHD1_DEVSCOPE1_BUS,
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.devfun = DRHD1_DEVSCOPE1_PATH,
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},
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};
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static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {
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{
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.dev_cnt = DRHD0_DEV_CNT,
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.segment = DRHD0_SEGMENT,
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.flags = DRHD0_FLAGS,
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.reg_base_addr = DRHD0_REG_BASE,
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.ignore = DRHD0_IGNORE,
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.devices = drhd0_dev_scope
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},
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{
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.dev_cnt = DRHD1_DEV_CNT,
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.segment = DRHD1_SEGMENT,
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.flags = DRHD1_FLAGS,
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.reg_base_addr = DRHD1_REG_BASE,
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.ignore = DRHD1_IGNORE,
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.devices = drhd1_dev_scope
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},
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};
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struct dmar_info plat_dmar_info = {
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.drhd_count = DRHD_COUNT,
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.drhd_units = drhd_info_array,
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};
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#ifdef CONFIG_RDT_ENABLED
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struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
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struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
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struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
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#endif
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static const struct cpu_cx_data board_cpu_cx[3] = {
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x33UL}, 0x02U, 0x97U, 0x00U}, /* C2 */
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{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x60UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */
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};
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static const struct cpu_px_data board_cpu_px[10] = {
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{0x835UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002E00UL, 0x002E00UL}, /* P0 */
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{0x834UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001500UL, 0x001500UL}, /* P1 */
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{0x7D0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001400UL, 0x001400UL}, /* P2 */
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{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL}, /* P3 */
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{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P4 */
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{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P5 */
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{0x640UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001000UL, 0x001000UL}, /* P6 */
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{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P7 */
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{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P8 */
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{0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */
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};
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const struct cpu_state_table board_cpu_state_tbl = {
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"Intel(R) Core(TM) i7-8565U CPU @ 1.80GHz",
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{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,
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(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}
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};
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const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
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const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];
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