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https://github.com/projectacrn/acrn-hypervisor.git
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e8b25bbbdb
so that vm_configurations.h/vm_configurations.c are consistent for same scenario Upload configuration source code for: Board scenarios whl-ipc-i5 industry, hybrid, hybrid_rt, logical_partiton whl-ipc-i7 industry, hybrid, hybrid_rt, logical_partiton ehl-crb-b industry, hybrid, hybrid_rt, logical_partition nuc7i7dnb industry, hybrid, logical_partition Tracked-On: #5229 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MISC_CFG_H
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#define MISC_CFG_H
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#define SOS_ROOTFS "root=/dev/sda3 "
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#define SOS_CONSOLE "console=ttyS0 "
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#define SOS_COM1_BASE 0x3F8U
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#define SOS_COM1_IRQ 4U
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#define SOS_COM2_BASE 0x2F8U
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#define SOS_COM2_IRQ 3U
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#define SOS_BOOTARGS_DIFF "rw " \
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"rootwait " \
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"console=tty0 " \
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"consoleblank=0 " \
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"no_timer_check " \
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"quiet " \
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"loglevel=3 " \
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"i915.nuclear_pageflip=1 " \
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"hvlog=2M@0xe00000 " \
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"memmap=0x200000$0xe00000 " \
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"maxcpus=3"
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#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
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#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
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#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
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#ifdef CONFIG_RDT_ENABLED
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/*
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* The maximum CLOS that is allowed by ACRN hypervisor,
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* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
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* among all supported RDT resources in the platform. In other words, it is
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* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
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* CLOS allocations between all the RDT resources.
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*/
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#define HV_SUPPORTED_MAX_CLOS 0U
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/*
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* Max number of Cache Mask entries corresponding to each CLOS.
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* This can vary if CDP is enabled vs disabled, as each CLOS entry
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* will have corresponding cache mask values for Data and Code when
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* CDP is enabled.
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*/
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#define MAX_MBA_CLOS_NUM_ENTRIES 0U
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/* Max number of MBA delay entries corresponding to each CLOS. */
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#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
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#endif
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#define VM0_PASSTHROUGH_TPM
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#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL
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#define VM0_TPM_BUFFER_BASE_ADDR_GPA 0xFED40000UL
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#define VM0_TPM_BUFFER_SIZE 0x5000UL
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#define VM0_CONFIG_PCI_DEV_NUM 1U
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#define VM0_PT_INTX_NUM 0U
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#endif /* MISC_CFG_H */
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