mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-02 05:34:04 +00:00
08139c34f7
To handle cpu down/up dynamically, arcn needs to support vmx off/on
dynamically. Following changes is introduced:
vmx_off will be used when down AP. It does:
- vmclear the mapped vcpu
- off vmx.
exec_vmxon_instr is updated to handle start and up AP both. It does
- if vmx was on on AP, load the vmxon_region saved. Otherwise,
allocate vmxon_region.
- if there is mapped vcpu, vmptrld mapped vcpu.
Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Signed-off-by: Yin Fegnwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
438 lines
19 KiB
C
438 lines
19 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VMX_H_
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#define VMX_H_
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/* 16-bit control fields */
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#define VMX_VPID 0x00000000
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/* 16-bit guest-state fields */
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#define VMX_GUEST_ES_SEL 0x00000800
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#define VMX_GUEST_CS_SEL 0x00000802
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#define VMX_GUEST_SS_SEL 0x00000804
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#define VMX_GUEST_DS_SEL 0x00000806
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#define VMX_GUEST_FS_SEL 0x00000808
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#define VMX_GUEST_GS_SEL 0x0000080a
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#define VMX_GUEST_LDTR_SEL 0x0000080c
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#define VMX_GUEST_TR_SEL 0x0000080e
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#define VMX_GUEST_INTR_STATUS 0x00000810
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/* 16-bit host-state fields */
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#define VMX_HOST_ES_SEL 0x00000c00
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#define VMX_HOST_CS_SEL 0x00000c02
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#define VMX_HOST_SS_SEL 0x00000c04
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#define VMX_HOST_DS_SEL 0x00000c06
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#define VMX_HOST_FS_SEL 0x00000c08
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#define VMX_HOST_GS_SEL 0x00000c0a
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#define VMX_HOST_TR_SEL 0x00000c0c
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/* 64-bit control fields */
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#define VMX_IO_BITMAP_A_FULL 0x00002000
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#define VMX_IO_BITMAP_A_HIGH 0x00002001
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#define VMX_IO_BITMAP_B_FULL 0x00002002
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#define VMX_IO_BITMAP_B_HIGH 0x00002003
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#define VMX_MSR_BITMAP_FULL 0x00002004
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#define VMX_MSR_BITMAP_HIGH 0x00002005
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#define VMX_EXIT_MSR_STORE_ADDR_FULL 0x00002006
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#define VMX_EXIT_MSR_STORE_ADDR_HIGH 0x00002007
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#define VMX_EXIT_MSR_LOAD_ADDR_FULL 0x00002008
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#define VMX_EXIT_MSR_LOAD_ADDR_HIGH 0x00002009
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#define VMX_ENTRY_MSR_LOAD_ADDR_FULL 0x0000200a
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#define VMX_ENTRY_MSR_LOAD_ADDR_HIGH 0x0000200b
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#define VMX_EXECUTIVE_VMCS_PTR_FULL 0x0000200c
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#define VMX_EXECUTIVE_VMCS_PTR_HIGH 0x0000200d
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#define VMX_TSC_OFFSET_FULL 0x00002010
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#define VMX_TSC_OFFSET_HIGH 0x00002011
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#define VMX_VIRTUAL_APIC_PAGE_ADDR_FULL 0x00002012
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#define VMX_VIRTUAL_APIC_PAGE_ADDR_HIGH 0x00002013
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#define VMX_APIC_ACCESS_ADDR_FULL 0x00002014
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#define VMX_APIC_ACCESS_ADDR_HIGH 0x00002015
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#define VMX_EPT_POINTER_FULL 0x0000201A
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#define VMX_EPT_POINTER_HIGH 0x0000201B
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#define VMX_EOI_EXIT0_FULL 0x0000201C
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#define VMX_EOI_EXIT0_HIGH 0x0000201D
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#define VMX_EOI_EXIT1_FULL 0x0000201E
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#define VMX_EOI_EXIT1_HIGH 0x0000201F
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#define VMX_EOI_EXIT2_FULL 0x00002020
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#define VMX_EOI_EXIT2_HIGH 0x00002021
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#define VMX_EOI_EXIT3_FULL 0x00002022
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#define VMX_EOI_EXIT3_HIGH 0x00002023
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#define VMX_EOI_EXIT(vector) (VMX_EOI_EXIT0_FULL + ((vector) / 64) * 2)
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#define VMX_XSS_EXITING_BITMAP_FULL 0x0000202C
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#define VMX_XSS_EXITING_BITMAP_HIGH 0x0000202D
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/* 64-bit read-only data fields */
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#define VMX_GUEST_PHYSICAL_ADDR_FULL 0x00002400
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#define VMX_GUEST_PHYSICAL_ADDR_HIGH 0x00002401
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/* 64-bit guest-state fields */
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#define VMX_VMS_LINK_PTR_FULL 0x00002800
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#define VMX_VMS_LINK_PTR_HIGH 0x00002801
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#define VMX_GUEST_IA32_DEBUGCTL_FULL 0x00002802
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#define VMX_GUEST_IA32_DEBUGCTL_HIGH 0x00002803
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#define VMX_GUEST_IA32_PAT_FULL 0x00002804
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#define VMX_GUEST_IA32_PAT_HIGH 0x00002805
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#define VMX_GUEST_IA32_EFER_FULL 0x00002806
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#define VMX_GUEST_IA32_EFER_HIGH 0x00002807
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#define VMX_GUEST_IA32_PERF_CTL_FULL 0x00002808
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#define VMX_GUEST_IA32_PERF_CTL_HIGH 0x00002809
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#define VMX_GUEST_PDPTE0_FULL 0x0000280A
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#define VMX_GUEST_PDPTE0_HIGH 0x0000280B
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#define VMX_GUEST_PDPTE1_FULL 0x0000280C
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#define VMX_GUEST_PDPTE1_HIGH 0x0000280D
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#define VMX_GUEST_PDPTE2_FULL 0x0000280E
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#define VMX_GUEST_PDPTE2_HIGH 0x0000280F
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#define VMX_GUEST_PDPTE3_FULL 0x00002810
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#define VMX_GUEST_PDPTE3_HIGH 0x00002811
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/* 64-bit host-state fields */
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#define VMX_HOST_IA32_PAT_FULL 0x00002C00
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#define VMX_HOST_IA32_PAT_HIGH 0x00002C01
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#define VMX_HOST_IA32_EFER_FULL 0x00002C02
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#define VMX_HOST_IA32_EFER_HIGH 0x00002C03
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#define VMX_HOST_IA32_PERF_CTL_FULL 0x00002C04
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#define VMX_HOST_IA32_PERF_CTL_HIGH 0x00002C05
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/* 32-bit control fields */
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#define VMX_PIN_VM_EXEC_CONTROLS 0x00004000
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#define VMX_PROC_VM_EXEC_CONTROLS 0x00004002
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#define VMX_EXCEPTION_BITMAP 0x00004004
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#define VMX_PF_ERROR_CODE_MASK 0x00004006
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#define VMX_PF_ERROR_CODE_MATCH 0x00004008
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#define VMX_CR3_TARGET_COUNT 0x0000400a
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#define VMX_EXIT_CONTROLS 0x0000400c
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#define VMX_EXIT_MSR_STORE_COUNT 0x0000400e
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#define VMX_EXIT_MSR_LOAD_COUNT 0x00004010
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#define VMX_ENTRY_CONTROLS 0x00004012
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#define VMX_ENTRY_MSR_LOAD_COUNT 0x00004014
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#define VMX_ENTRY_INT_INFO_FIELD 0x00004016
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#define VMX_ENTRY_EXCEPTION_ERROR_CODE 0x00004018
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#define VMX_ENTRY_INSTR_LENGTH 0x0000401a
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#define VMX_TPR_THRESHOLD 0x0000401c
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#define VMX_PROC_VM_EXEC_CONTROLS2 0x0000401E
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#define VMX_PLE_GAP 0x00004020
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#define VMX_PLE_WINDOW 0x00004022
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/* 32-bit read-only data fields */
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#define VMX_INSTR_ERROR 0x00004400
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#define VMX_EXIT_REASON 0x00004402
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#define VMX_EXIT_INT_INFO 0x00004404
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#define VMX_EXIT_INT_ERROR_CODE 0x00004406
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#define VMX_IDT_VEC_INFO_FIELD 0x00004408
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#define VMX_IDT_VEC_ERROR_CODE 0x0000440a
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#define VMX_EXIT_INSTR_LEN 0x0000440c
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#define VMX_INSTR_INFO 0x0000440e
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/* 32-bit guest-state fields */
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#define VMX_GUEST_ES_LIMIT 0x00004800
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#define VMX_GUEST_CS_LIMIT 0x00004802
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#define VMX_GUEST_SS_LIMIT 0x00004804
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#define VMX_GUEST_DS_LIMIT 0x00004806
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#define VMX_GUEST_FS_LIMIT 0x00004808
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#define VMX_GUEST_GS_LIMIT 0x0000480a
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#define VMX_GUEST_LDTR_LIMIT 0x0000480c
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#define VMX_GUEST_TR_LIMIT 0x0000480e
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#define VMX_GUEST_GDTR_LIMIT 0x00004810
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#define VMX_GUEST_IDTR_LIMIT 0x00004812
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#define VMX_GUEST_ES_ATTR 0x00004814
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#define VMX_GUEST_CS_ATTR 0x00004816
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#define VMX_GUEST_SS_ATTR 0x00004818
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#define VMX_GUEST_DS_ATTR 0x0000481a
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#define VMX_GUEST_FS_ATTR 0x0000481c
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#define VMX_GUEST_GS_ATTR 0x0000481e
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#define VMX_GUEST_LDTR_ATTR 0x00004820
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#define VMX_GUEST_TR_ATTR 0x00004822
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#define VMX_GUEST_INTERRUPTIBILITY_INFO 0x00004824
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#define VMX_GUEST_ACTIVITY_STATE 0x00004826
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#define VMX_GUEST_SMBASE 0x00004828
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#define VMX_GUEST_IA32_SYSENTER_CS 0x0000482a
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#define VMX_GUEST_TIMER 0x0000482E
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/* 32-bit host-state fields */
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#define VMX_HOST_IA32_SYSENTER_CS 0x00004c00
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/* natural-width control fields */
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#define VMX_CR0_MASK 0x00006000
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#define VMX_CR4_MASK 0x00006002
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#define VMX_CR0_READ_SHADOW 0x00006004
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#define VMX_CR4_READ_SHADOW 0x00006006
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#define VMX_CR3_TARGET_0 0x00006008
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#define VMX_CR3_TARGET_1 0x0000600a
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#define VMX_CR3_TARGET_2 0x0000600c
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#define VMX_CR3_TARGET_3 0x0000600e
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/* natural-width read-only data fields */
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#define VMX_EXIT_QUALIFICATION 0x00006400
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#define VMX_IO_RCX 0x00006402
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#define VMX_IO_RDI 0x00006406
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#define VMX_GUEST_LINEAR_ADDR 0x0000640a
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/* natural-width guest-state fields */
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#define VMX_GUEST_CR0 0x00006800
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#define VMX_GUEST_CR3 0x00006802
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#define VMX_GUEST_CR4 0x00006804
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#define VMX_GUEST_ES_BASE 0x00006806
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#define VMX_GUEST_CS_BASE 0x00006808
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#define VMX_GUEST_SS_BASE 0x0000680a
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#define VMX_GUEST_DS_BASE 0x0000680c
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#define VMX_GUEST_FS_BASE 0x0000680e
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#define VMX_GUEST_GS_BASE 0x00006810
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#define VMX_GUEST_LDTR_BASE 0x00006812
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#define VMX_GUEST_TR_BASE 0x00006814
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#define VMX_GUEST_GDTR_BASE 0x00006816
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#define VMX_GUEST_IDTR_BASE 0x00006818
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#define VMX_GUEST_DR7 0x0000681a
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#define VMX_GUEST_RSP 0x0000681c
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#define VMX_GUEST_RIP 0x0000681e
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#define VMX_GUEST_RFLAGS 0x00006820
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#define VMX_GUEST_PENDING_DEBUG_EXCEPT 0x00006822
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#define VMX_GUEST_IA32_SYSENTER_ESP 0x00006824
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#define VMX_GUEST_IA32_SYSENTER_EIP 0x00006826
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/* natural-width host-state fields */
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#define VMX_HOST_CR0 0x00006c00
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#define VMX_HOST_CR3 0x00006c02
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#define VMX_HOST_CR4 0x00006c04
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#define VMX_HOST_FS_BASE 0x00006c06
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#define VMX_HOST_GS_BASE 0x00006c08
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#define VMX_HOST_TR_BASE 0x00006c0a
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#define VMX_HOST_GDTR_BASE 0x00006c0c
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#define VMX_HOST_IDTR_BASE 0x00006c0e
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#define VMX_HOST_IA32_SYSENTER_ESP 0x00006c10
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#define VMX_HOST_IA32_SYSENTER_EIP 0x00006c12
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#define VMX_HOST_RSP 0x00006c14
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#define VMX_HOST_RIP 0x00006c16
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/*
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* Basic VM exit reasons
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*/
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#define VMX_EXIT_REASON_EXCEPTION_OR_NMI 0x00000000
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#define VMX_EXIT_REASON_EXTERNAL_INTERRUPT 0x00000001
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#define VMX_EXIT_REASON_TRIPLE_FAULT 0x00000002
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#define VMX_EXIT_REASON_INIT_SIGNAL 0x00000003
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#define VMX_EXIT_REASON_STARTUP_IPI 0x00000004
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#define VMX_EXIT_REASON_IO_SMI 0x00000005
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#define VMX_EXIT_REASON_OTHER_SMI 0x00000006
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#define VMX_EXIT_REASON_INTERRUPT_WINDOW 0x00000007
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#define VMX_EXIT_REASON_NMI_WINDOW 0x00000008
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#define VMX_EXIT_REASON_TASK_SWITCH 0x00000009
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#define VMX_EXIT_REASON_CPUID 0x0000000A
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#define VMX_EXIT_REASON_GETSEC 0x0000000B
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#define VMX_EXIT_REASON_HLT 0x0000000C
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#define VMX_EXIT_REASON_INVD 0x0000000D
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#define VMX_EXIT_REASON_INVLPG 0x0000000E
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#define VMX_EXIT_REASON_RDPMC 0x0000000F
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#define VMX_EXIT_REASON_RDTSC 0x00000010
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#define VMX_EXIT_REASON_RSM 0x00000011
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#define VMX_EXIT_REASON_VMCALL 0x00000012
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#define VMX_EXIT_REASON_VMCLEAR 0x00000013
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#define VMX_EXIT_REASON_VMLAUNCH 0x00000014
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#define VMX_EXIT_REASON_VMPTRLD 0x00000015
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#define VMX_EXIT_REASON_VMPTRST 0x00000016
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#define VMX_EXIT_REASON_VMREAD 0x00000017
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#define VMX_EXIT_REASON_VMRESUME 0x00000018
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#define VMX_EXIT_REASON_VMWRITE 0x00000019
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#define VMX_EXIT_REASON_VMXOFF 0x0000001A
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#define VMX_EXIT_REASON_VMXON 0x0000001B
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#define VMX_EXIT_REASON_CR_ACCESS 0x0000001C
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#define VMX_EXIT_REASON_DR_ACCESS 0x0000001D
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#define VMX_EXIT_REASON_IO_INSTRUCTION 0x0000001E
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#define VMX_EXIT_REASON_RDMSR 0x0000001F
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#define VMX_EXIT_REASON_WRMSR 0x00000020
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#define VMX_EXIT_REASON_ENTRY_FAILURE_INVALID_GUEST_STATE 0x00000021
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#define VMX_EXIT_REASON_ENTRY_FAILURE_MSR_LOADING 0x00000022
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/* entry 0x23 (35) is missing */
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#define VMX_EXIT_REASON_MWAIT 0x00000024
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#define VMX_EXIT_REASON_MONITOR_TRAP 0x00000025
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/* entry 0x26 (38) is missing */
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#define VMX_EXIT_REASON_MONITOR 0x00000027
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#define VMX_EXIT_REASON_PAUSE 0x00000028
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#define VMX_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK 0x00000029
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/* entry 0x2A (42) is missing */
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#define VMX_EXIT_REASON_TPR_BELOW_THRESHOLD 0x0000002B
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#define VMX_EXIT_REASON_APIC_ACCESS 0x0000002C
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#define VMX_EXIT_REASON_VIRTUALIZED_EOI 0x0000002D
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#define VMX_EXIT_REASON_GDTR_IDTR_ACCESS 0x0000002E
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#define VMX_EXIT_REASON_LDTR_TR_ACCESS 0x0000002F
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#define VMX_EXIT_REASON_EPT_VIOLATION 0x00000030
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#define VMX_EXIT_REASON_EPT_MISCONFIGURATION 0x00000031
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#define VMX_EXIT_REASON_INVEPT 0x00000032
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#define VMX_EXIT_REASON_RDTSCP 0x00000033
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#define VMX_EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED 0x00000034
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#define VMX_EXIT_REASON_INVVPID 0x00000035
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#define VMX_EXIT_REASON_WBINVD 0x00000036
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#define VMX_EXIT_REASON_XSETBV 0x00000037
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#define VMX_EXIT_REASON_APIC_WRITE 0x00000038
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/* VMX execution control bits (pin based) */
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#define VMX_PINBASED_CTLS_IRQ_EXIT (1<<0)
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#define VMX_PINBASED_CTLS_NMI_EXIT (1<<3)
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#define VMX_PINBASED_CTLS_VIRT_NMI (1<<5)
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#define VMX_PINBASED_CTLS_ENABLE_PTMR (1<<6)
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#define VMX_PINBASED_CTLS_POST_IRQ (1<<7)
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/* VMX execution control bits (processor based) */
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#define VMX_PROCBASED_CTLS_IRQ_WIN (1<<2)
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#define VMX_PROCBASED_CTLS_TSC_OFF (1<<3)
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#define VMX_PROCBASED_CTLS_HLT (1<<7)
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#define VMX_PROCBASED_CTLS_INVLPG (1<<9)
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#define VMX_PROCBASED_CTLS_MWAIT (1<<10)
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#define VMX_PROCBASED_CTLS_RDPMC (1<<11)
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#define VMX_PROCBASED_CTLS_RDTSC (1<<12)
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#define VMX_PROCBASED_CTLS_CR3_LOAD (1<<15)
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#define VMX_PROCBASED_CTLS_CR3_STORE (1<<16)
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#define VMX_PROCBASED_CTLS_CR8_LOAD (1<<19)
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#define VMX_PROCBASED_CTLS_CR8_STORE (1<<20)
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#define VMX_PROCBASED_CTLS_TPR_SHADOW (1<<21)
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#define VMX_PROCBASED_CTLS_NMI_WINEXIT (1<<22)
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#define VMX_PROCBASED_CTLS_MOV_DR (1<<23)
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#define VMX_PROCBASED_CTLS_UNCOND_IO (1<<24)
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#define VMX_PROCBASED_CTLS_IO_BITMAP (1<<25)
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#define VMX_PROCBASED_CTLS_MON_TRAP (1<<27)
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#define VMX_PROCBASED_CTLS_MSR_BITMAP (1<<28)
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#define VMX_PROCBASED_CTLS_MONITOR (1<<29)
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#define VMX_PROCBASED_CTLS_PAUSE (1<<30)
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#define VMX_PROCBASED_CTLS_SECONDARY (1<<31)
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#define VMX_PROCBASED_CTLS2_VAPIC (1<<0)
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#define VMX_PROCBASED_CTLS2_EPT (1<<1)
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#define VMX_PROCBASED_CTLS2_DESC_TABLE (1<<2)
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#define VMX_PROCBASED_CTLS2_RDTSCP (1<<3)
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#define VMX_PROCBASED_CTLS2_VX2APIC (1<<4)
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#define VMX_PROCBASED_CTLS2_VPID (1<<5)
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#define VMX_PROCBASED_CTLS2_WBINVD (1<<6)
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#define VMX_PROCBASED_CTLS2_UNRESTRICT (1<<7)
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#define VMX_PROCBASED_CTLS2_VAPIC_REGS (1<<8)
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#define VMX_PROCBASED_CTLS2_VIRQ (1<<9)
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#define VMX_PROCBASED_CTLS2_PAUSE_LOOP (1<<10)
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#define VMX_PROCBASED_CTLS2_RDRAND (1<<11)
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#define VMX_PROCBASED_CTLS2_INVPCID (1<<12)
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#define VMX_PROCBASED_CTLS2_VM_FUNCS (1<<13)
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#define VMX_PROCBASED_CTLS2_VMCS_SHADW (1<<14)
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#define VMX_PROCBASED_CTLS2_RDSEED (1<<16)
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#define VMX_PROCBASED_CTLS2_EPT_VE (1<<18)
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#define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1<<20)
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/* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */
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#define VMX_EPT_EXECUTE_ONLY (1 << 0)
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#define VMX_EPT_PAGE_WALK_4 (1 << 6)
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#define VMX_EPT_PAGE_WALK_5 (1 << 7)
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#define VMX_EPTP_UC (1 << 8)
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#define VMX_EPTP_WB (1 << 14)
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#define VMX_EPT_2MB_PAGE (1 << 16)
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#define VMX_EPT_1GB_PAGE (1 << 17)
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#define VMX_EPT_INVEPT (1 << 20)
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#define VMX_EPT_AD (1 << 21)
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#define VMX_EPT_INVEPT_SINGLE_CONTEXT (1 << 25)
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#define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1 << 26)
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#define VMX_MIN_NR_VPID 1
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#define VMX_MAX_NR_VPID (1 << 5)
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#define VMX_VPID_TYPE_INDIVIDUAL_ADDR 0
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#define VMX_VPID_TYPE_SINGLE_CONTEXT 1
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#define VMX_VPID_TYPE_ALL_CONTEXT 2
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#define VMX_VPID_TYPE_SINGLE_NON_GLOBAL 3
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#define VMX_VPID_INVVPID (1 << 0) /* (32 - 32) */
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#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1 << 8) /* (40 - 32) */
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#define VMX_VPID_INVVPID_SINGLE_CONTEXT (1 << 9) /* (41 - 32) */
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#define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1 << 10) /* (42 - 32) */
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#define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1 << 11) /* (43 - 32) */
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#define VMX_EPT_MT_EPTE_SHIFT 3
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#define VMX_EPTP_PWL_MASK 0x38
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#define VMX_EPTP_PWL_4 0x18
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#define VMX_EPTP_PWL_5 0x20
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#define VMX_EPTP_AD_ENABLE_BIT (1 << 6)
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#define VMX_EPTP_MT_MASK 0x7
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#define VMX_EPTP_MT_WB 0x6
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#define VMX_EPTP_MT_UC 0x0
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/* VMX exit control bits */
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#define VMX_EXIT_CTLS_SAVE_DBG (1<<2)
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#define VMX_EXIT_CTLS_HOST_ADDR64 (1<<9)
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#define VMX_EXIT_CTLS_LOAD_PERF (1<<12)
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#define VMX_EXIT_CTLS_ACK_IRQ (1<<15)
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#define VMX_EXIT_CTLS_SAVE_PAT (1<<18)
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#define VMX_EXIT_CTLS_LOAD_PAT (1<<19)
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#define VMX_EXIT_CTLS_SAVE_EFER (1<<20)
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#define VMX_EXIT_CTLS_LOAD_EFER (1<<21)
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#define VMX_EXIT_CTLS_SAVE_PTMR (1<<22)
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/* VMX entry control bits */
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#define VMX_ENTRY_CTLS_LOAD_DBG (1<<2)
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#define VMX_ENTRY_CTLS_IA32E_MODE (1<<9)
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#define VMX_ENTRY_CTLS_ENTRY_SMM (1<<10)
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#define VMX_ENTRY_CTLS_DEACT_DUAL (1<<11)
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#define VMX_ENTRY_CTLS_LOAD_PERF (1<<13)
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#define VMX_ENTRY_CTLS_LOAD_PAT (1<<14)
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#define VMX_ENTRY_CTLS_LOAD_EFER (1<<15)
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|
|
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/* VMX entry/exit Interrupt info */
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#define VMX_INT_INFO_ERR_CODE_VALID (1<<11)
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#define VMX_INT_INFO_VALID (1<<31)
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|
#define VMX_INT_TYPE_MASK (0x700)
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|
#define VMX_INT_TYPE_EXT_INT 0
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|
#define VMX_INT_TYPE_NMI 2
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|
#define VMX_INT_TYPE_HW_EXP 3
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|
#define VMX_INT_TYPE_SW_EXP 6
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|
|
/*VM exit qulifications for APIC-access
|
|
* Access type:
|
|
* 0 = linear access for a data read during instruction execution
|
|
* 1 = linear access for a data write during instruction execution
|
|
* 2 = linear access for an instruction fetch
|
|
* 3 = linear access (read or write) during event delivery
|
|
* 10 = guest-physical access during event delivery
|
|
* 15 = guest-physical access for an instructon fetch or during
|
|
* instruction execution
|
|
*/
|
|
#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xF)
|
|
#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFF)
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|
|
|
|
|
#define VM_SUCCESS 0
|
|
#define VM_FAIL -1
|
|
|
|
#define VMX_VMENTRY_FAIL 0x80000000
|
|
|
|
#ifndef ASSEMBLER
|
|
|
|
#define RFLAGS_C (1<<0)
|
|
#define RFLAGS_Z (1<<6)
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|
|
|
/* CR0 bits hv want to trap to track status change */
|
|
#define CR0_TRAP_MASK (CR0_PE | CR0_PG | CR0_WP)
|
|
#define CR0_RESERVED_MASK ~(CR0_PG | CR0_CD | CR0_NW | CR0_AM | CR0_WP | \
|
|
CR0_NE | CR0_ET | CR0_TS | CR0_EM | CR0_MP | CR0_PE)
|
|
|
|
/* CR4 bits hv want to trap to track status change */
|
|
#define CR4_TRAP_MASK (CR4_PSE | CR4_PAE)
|
|
|
|
#define VMX_SUPPORT_UNRESTRICTED_GUEST (1<<5)
|
|
|
|
/* External Interfaces */
|
|
int exec_vmxon_instr(uint32_t pcpu_id);
|
|
uint64_t exec_vmread(uint32_t field);
|
|
uint64_t exec_vmread64(uint32_t field_full);
|
|
void exec_vmwrite(uint32_t field, uint64_t value);
|
|
void exec_vmwrite64(uint32_t field_full, uint64_t value);
|
|
int init_vmcs(struct vcpu *vcpu);
|
|
|
|
int vmx_off(int pcpu_id);
|
|
int vmx_restart(int pcpu_id);
|
|
|
|
int exec_vmclear(void *addr);
|
|
int exec_vmptrld(void *addr);
|
|
|
|
int vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0);
|
|
int vmx_write_cr3(struct vcpu *vcpu, uint64_t cr3);
|
|
int vmx_write_cr4(struct vcpu *vcpu, uint64_t cr4);
|
|
|
|
static inline uint8_t get_vcpu_mode(struct vcpu *vcpu)
|
|
{
|
|
return vcpu->arch_vcpu.cpu_mode;
|
|
}
|
|
|
|
static inline bool cpu_has_vmx_unrestricted_guest_cap(void)
|
|
{
|
|
return !!(msr_read(MSR_IA32_VMX_MISC) & VMX_SUPPORT_UNRESTRICTED_GUEST);
|
|
}
|
|
|
|
typedef struct _descriptor_table_{
|
|
uint16_t limit;
|
|
uint64_t base;
|
|
}__attribute__((packed)) descriptor_table;
|
|
#endif /* ASSEMBLER */
|
|
|
|
#endif /* VMX_H_ */
|