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2c86795fa8
The coding guideline rule C-TY-24 requires that 'cast shall not be performed on a function pointer'. This patch removes a duplicated explicit cast on timer_expired_handler in tsc_deadline_timer.c. This patch has no semantic impacts. Tracked-On: #6776 Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/*
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <softirq.h>
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#include <irq.h>
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#include <logmsg.h>
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#include <asm/cpu.h>
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#include <asm/msr.h>
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#include <asm/irq.h>
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#include <asm/apicreg.h>
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#include <hw/hw_timer.h>
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/* run in interrupt context */
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static void timer_expired_handler(__unused uint32_t irq, __unused void *data)
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{
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fire_softirq(SOFTIRQ_TIMER);
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}
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void set_hw_timeout(uint64_t timeout)
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{
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msr_write(MSR_IA32_TSC_DEADLINE, timeout);
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}
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void init_hw_timer(void)
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{
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int32_t retval = 0;
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if (get_pcpu_id() == BSP_CPU_ID) {
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retval = request_irq(TIMER_IRQ, timer_expired_handler, NULL, IRQF_NONE);
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if (retval < 0) {
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pr_err("Timer setup failed");
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}
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}
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if (retval >= 0) {
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uint32_t val = TIMER_VECTOR;
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val |= APIC_LVTT_TM_TSCDLT; /* TSC deadline and unmask */
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msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, val);
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/* SDM 10.5.4.1: In x2APIC mode, the processor ensures the
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ordering of this write and any subsequent WRMSR to the
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deadline; no fencing is required. */
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/* disarm timer */
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msr_write(MSR_IA32_TSC_DEADLINE, 0UL);
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}
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}
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