mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2026-07-27 08:50:58 +00:00
8c2e8a6b5d
Unlike x86 which explicitly distinguishes guest traps and host traps (VM exits vs. IDT trap gates), risc-v unifies them to a single trap gate with bits in multiple CSRs representing the privilege mode before the trap. This commit follows this design. Due to this change the arch_vcpu_thread in risc-v was basically abandoned, and used only as a first-time entry point to guest, with the rest of the original x86 arch_vcpu_thread being re-implemented following above single-entry design. Save/restore routine is also being re-implemented to account for both hs-mode traps and v-mode traps. sscratch is used to mark the place where the context is being saved to/restored from. When sscratch is zero at the time of the trap, the context is saved into host stack. When sscratch is non-zero, the context is saved to vcpu->arch.regs (similar for restore). Tracked-On: #8841 Signed-off-by: Yifan Liu <yifan1.liu@intel.com> Signed-off-by: Haicheng Li <haicheng.li@intel.com> Acked-by: Wang Yu1 <yu1.wang@intel.com>
101 lines
2.1 KiB
C
101 lines
2.1 KiB
C
/*
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* Copyright (C) 2023-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#include <asm/csr.h>
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#include <asm/trap.h>
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#include <irq.h>
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#include <vcpu.h>
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#include <cpu.h>
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#include <logmsg.h>
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#include <notify.h>
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#include <debug/dump.h>
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#include <asm/guest/vcpu_exit.h>
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static void unexpected_trap_handler(const struct intr_excp_ctx *ctx)
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{
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pr_err("Unexpected S mode trap 0x%lx\n", ctx->regs.cause);
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/* Halt the CPU */
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cpu_dead();
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}
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/* IRQ 1 - Supervisor software interrupt handler */
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void s_sw_irq_handler(__unused uint32_t irq, __unused void *data)
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{
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cpu_csr_clear(CSR_SIP, IP_IE_SSI);
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handle_smp_call();
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}
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static void dispatch_exception(const struct intr_excp_ctx *ctx)
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{
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uint16_t pcpu_id = get_pcpu_id();
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/* Dump exception context */
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dump_exception(ctx, pcpu_id);
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/* Halt the CPU */
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cpu_dead();
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}
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static void riscv_do_irq(const char *name, uint32_t src_id)
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{
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uint32_t acrn_irq = riscv_domain_get_acrn_irq(name, src_id);
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if (riscv_is_valid_acrn_irq(acrn_irq)) {
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do_irq(acrn_irq);
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} else {
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pr_err("%s: Invalid IRQ %d\n", __func__, acrn_irq);
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}
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}
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void dispatch_interrupt(const struct intr_excp_ctx *ctx)
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{
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uint64_t trap_cause = ctx->regs.cause & (~TRAP_CAUSE_INTERRUPT_BITMASK);
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switch (trap_cause) {
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case TRAP_CAUSE_IRQ_S_EXT:
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/**
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* Handle TRAP_CAUSE_IRQ_S_EXT as a special case.
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* Because recursion shall be avoided to comply with FuSa.
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*
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* FIXME:
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* Abstract PLIC/AIA as a irqchip that implement a get_irq API
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* to do the mapping between irq_num and PLIC source id or AIA's MSI.
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*
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* Pseudo-code:
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* while ((src_id = get_pending_irq_from_chip()) != NONE) {
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* riscv_do_irq(RISCV_IRQD_PLIC, src_id);
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* }
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*
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*/
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unexpected_trap_handler(ctx);
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break;
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case TRAP_CAUSE_IRQ_S_SOFT:
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/* intentional fall-through */
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case TRAP_CAUSE_IRQ_S_TIMER:
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riscv_do_irq(RISCV_IRQD_CPU, trap_cause);
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break;
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default:
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unexpected_trap_handler(ctx);
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break;
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}
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}
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void dispatch_trap(const struct intr_excp_ctx *ctx)
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{
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if ((ctx->regs.cause & TRAP_CAUSE_INTERRUPT_BITMASK) == 0UL) {
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dispatch_exception(ctx);
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} else {
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dispatch_interrupt(ctx);
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}
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}
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