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https://github.com/projectacrn/acrn-hypervisor.git
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bae19f5f1f
Original interrupt context save/restore routine saves to/restore from per-cpu stack. This commit modifies it to support saving to/restoring from address pointed to by sscratch register. When sscratch is 0, the assembly is functionally equivalent to the old version (save to/restore from per-cpu stack) When sscratch is not 0, the assembly saves to/restores from the place that sscratch points to. hstatus is also added to the trap frame as this affects the virtual mode the trap returns to. Tracked-On: #8841 Signed-off-by: Yifan Liu <yifan1.liu@intel.com> Signed-off-by: Haicheng Li <haicheng.li@intel.com> Acked-by: Wang Yu1 <yu1.wang@intel.com>
193 lines
4.3 KiB
C
193 lines
4.3 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#ifndef ASSEMBLER
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#include <types.h>
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#include <lib/util.h>
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#include <logmsg.h>
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#include <board_info.h>
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#include <barrier.h>
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#include <asm/csr.h>
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/* The following symbols must remain consistent:
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* - CPU_REGS_OFFSET_* macros in `include/arch/riscv/asm/offset.h`
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* - struct cpu_regs
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* - cpu_ctx_save/cpu_ctx_restore macros used in assembly
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*/
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struct cpu_regs {
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/* General purpose registers. */
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uint64_t zero;
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uint64_t ra;
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uint64_t sp;
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uint64_t gp;
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uint64_t tp;
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uint64_t t0;
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uint64_t t1;
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uint64_t t2;
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uint64_t s0;
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uint64_t s1;
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uint64_t a0;
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uint64_t a1;
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uint64_t a2;
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uint64_t a3;
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uint64_t a4;
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uint64_t a5;
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uint64_t a6;
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uint64_t a7;
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uint64_t s2;
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uint64_t s3;
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uint64_t s4;
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uint64_t s5;
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uint64_t s6;
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uint64_t s7;
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uint64_t s8;
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uint64_t s9;
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uint64_t s10;
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uint64_t s11;
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uint64_t t3;
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uint64_t t4;
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uint64_t t5;
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uint64_t t6;
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/* Control and Status Registers (CSRs). */
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uint64_t epc;
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uint64_t status;
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uint64_t cause;
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uint64_t tval;
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uint64_t scratch;
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uint64_t hstatus;
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/* Host context. Used only in v-mode traps. */
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uint64_t host_tp;
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uint64_t host_gp;
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uint64_t exc_sp;
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};
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/* stack_frame is linked with the sequence of stack operation in arch_switch_to() */
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#define STACK_FRAME_OFFSET_RA 0x0
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#define STACK_FRAME_OFFSET_S0 0x8
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#define STACK_FRAME_OFFSET_S1 0x10
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#define STACK_FRAME_OFFSET_S2 0x18
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#define STACK_FRAME_OFFSET_S3 0x20
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#define STACK_FRAME_OFFSET_S4 0x28
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#define STACK_FRAME_OFFSET_S5 0x30
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#define STACK_FRAME_OFFSET_S6 0x38
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#define STACK_FRAME_OFFSET_S7 0x40
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#define STACK_FRAME_OFFSET_S8 0x48
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#define STACK_FRAME_OFFSET_S9 0x50
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#define STACK_FRAME_OFFSET_S10 0x58
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#define STACK_FRAME_OFFSET_S11 0x60
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#define STACK_FRAME_OFFSET_A0 0x68
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#define STACK_FRAME_OFFSET_STATUS 0x70
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struct stack_frame {
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uint64_t ra;
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uint64_t s0;
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uint64_t s1;
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uint64_t s2;
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uint64_t s3;
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uint64_t s4;
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uint64_t s5;
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uint64_t s6;
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uint64_t s7;
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uint64_t s8;
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uint64_t s9;
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uint64_t s10;
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uint64_t s11;
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uint64_t a0; /* thread_object parameter */
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uint64_t status;
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uint64_t magic;
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};
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#define cpu_relax() cpu_memory_barrier() /* TODO: replace with yield instruction */
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#define NR_CPUS MAX_PCPU_NUM
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#define LONG_BYTEORDER 3
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#define BYTES_PER_LONG (1 << LONG_BYTEORDER)
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#define BITS_PER_LONG (BYTES_PER_LONG << 3)
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/* Define CPU stack alignment */
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#define CPU_STACK_ALIGN 16UL
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/* In ACRN, struct per_cpu_region is a critical data structure
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* containing key per-CPU data frequently accessed via get_cpu_var().
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* We use the tp register to store the current logical pCPU ID to
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* facilitate efficient per-CPU data access. This design mirrors
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* the x86 implementation, which uses the dedicated MSR_IA32_SYSENTER_CS
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* MSR (unused by the hypervisor) for the same purpose.
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*/
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static inline uint16_t arch_get_pcpu_id(void)
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{
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register uint16_t pcpu_id asm ("tp");
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return pcpu_id;
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}
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static inline void arch_set_current_pcpu_id(uint16_t pcpu_id)
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{
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asm volatile ("mv tp, %0" : : "r" (pcpu_id) : "tp");
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}
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static inline void arch_asm_pause(void)
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{
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asm volatile ("pause" ::: "memory");
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}
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static inline void arch_local_irq_enable(void)
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{
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cpu_csr_set(CSR_SSTATUS, SSTATUS_SIE);
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}
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static inline void arch_local_irq_disable(void)
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{
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cpu_csr_clear(CSR_SSTATUS, SSTATUS_SIE);
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}
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static inline void arch_local_irq_save(uint64_t *flags_ptr)
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{
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*flags_ptr = cpu_csr_read_clear(CSR_SSTATUS, SSTATUS_SIE);
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}
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static inline void arch_local_irq_restore(uint64_t flags)
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{
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cpu_csr_set(CSR_SSTATUS, (flags & SSTATUS_SIE));
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}
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static inline void arch_pre_user_access(void)
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{
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cpu_csr_set(CSR_SSTATUS, SSTATUS_SUM);
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}
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static inline void arch_post_user_access(void)
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{
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cpu_csr_clear(CSR_SSTATUS, SSTATUS_SUM);
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}
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void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
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void init_percpu_hart_id(uint32_t bsp_hart_id);
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uint16_t get_pcpu_id_from_hart_id(uint32_t hart_id);
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/* FIXME: riscv dummy function */
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static inline bool need_offline(uint16_t pcpu_id)
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{
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(void)pcpu_id;
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return false;
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}
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/* FIXME: If RISC-V support sbuf, it should implement SMAP enable/disable APIs */
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static inline void stac(void) {}
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static inline void clac(void) {}
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#else /* ASSEMBLER */
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#include <asm/offset.h>
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#endif /* ASSEMBLER */
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#endif /* RISCV_CPU_H */
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