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https://github.com/projectacrn/acrn-hypervisor.git
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bae19f5f1f
Original interrupt context save/restore routine saves to/restore from per-cpu stack. This commit modifies it to support saving to/restoring from address pointed to by sscratch register. When sscratch is 0, the assembly is functionally equivalent to the old version (save to/restore from per-cpu stack) When sscratch is not 0, the assembly saves to/restores from the place that sscratch points to. hstatus is also added to the trap frame as this affects the virtual mode the trap returns to. Tracked-On: #8841 Signed-off-by: Yifan Liu <yifan1.liu@intel.com> Signed-off-by: Haicheng Li <haicheng.li@intel.com> Acked-by: Wang Yu1 <yu1.wang@intel.com>
67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
/*
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* Copyright (C) 2023-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef RISCV_OFFSET_H
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#define RISCV_OFFSET_H
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/* The following symbols must remain consistent:
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* - CPU_REGS_OFFSET_* macros in `include/arch/riscv/asm/offset.h`
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* - struct cpu_regs
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* - cpu_ctx_save/cpu_ctx_restore macros used in assembly
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*/
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/* General purpose registers. */
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#define CPU_REGS_OFFSET_ZERO 0x0
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#define CPU_REGS_OFFSET_RA 0x8
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#define CPU_REGS_OFFSET_SP 0x10
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#define CPU_REGS_OFFSET_GP 0x18
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#define CPU_REGS_OFFSET_TP 0x20
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#define CPU_REGS_OFFSET_T0 0x28
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#define CPU_REGS_OFFSET_T1 0x30
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#define CPU_REGS_OFFSET_T2 0x38
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#define CPU_REGS_OFFSET_S0 0x40
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#define CPU_REGS_OFFSET_S1 0x48
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#define CPU_REGS_OFFSET_A0 0x50
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#define CPU_REGS_OFFSET_A1 0x58
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#define CPU_REGS_OFFSET_A2 0x60
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#define CPU_REGS_OFFSET_A3 0x68
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#define CPU_REGS_OFFSET_A4 0x70
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#define CPU_REGS_OFFSET_A5 0x78
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#define CPU_REGS_OFFSET_A6 0x80
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#define CPU_REGS_OFFSET_A7 0x88
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#define CPU_REGS_OFFSET_S2 0x90
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#define CPU_REGS_OFFSET_S3 0x98
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#define CPU_REGS_OFFSET_S4 0xA0
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#define CPU_REGS_OFFSET_S5 0xA8
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#define CPU_REGS_OFFSET_S6 0xB0
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#define CPU_REGS_OFFSET_S7 0xB8
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#define CPU_REGS_OFFSET_S8 0xC0
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#define CPU_REGS_OFFSET_S9 0xC8
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#define CPU_REGS_OFFSET_S10 0xD0
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#define CPU_REGS_OFFSET_S11 0xD8
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#define CPU_REGS_OFFSET_T3 0xE0
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#define CPU_REGS_OFFSET_T4 0xE8
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#define CPU_REGS_OFFSET_T5 0xF0
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#define CPU_REGS_OFFSET_T6 0xF8
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/* Control and Status Registers (CSRs). */
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#define CPU_REGS_OFFSET_EPC 0x100
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#define CPU_REGS_OFFSET_STATUS 0x108
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#define CPU_REGS_OFFSET_CAUSE 0x110
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#define CPU_REGS_OFFSET_TVAL 0x118
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#define CPU_REGS_OFFSET_SCRATCH 0x120
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#define CPU_REGS_OFFSET_HSTATUS 0x128
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#define CPU_REGS_OFFSET_HOST_TP 0x130
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#define CPU_REGS_OFFSET_HOST_GP 0x138
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#define CPU_REGS_OFFSET_EXC_SP 0x140
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/* Total context area size (struct cpu_regs). */
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#define CPU_REGS_OFFSET_LAST (CPU_REGS_OFFSET_EXC_SP + 8)
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#endif /* RISCV_OFFSET_H */
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