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https://github.com/projectacrn/acrn-hypervisor.git
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789899d05f
- hardcode the devices' GSI info based on the platform
- reject the passthrough if the following requirement is not met
all the PCI devices that are sharing the same GSI should be assigned
to same VM to avoid physical GSI sharing between multiple VMs.
v4 -> v5
* Move the gsi_dev_mapping_tables definition in a separate file
* Add the GSI info that might be used by GPIO
* Update the HW name
v3 - > v4
* Refine the format of raw data to improve the readability
* Remove the redundant code when adding the new dev into the gsi
sharing group
v2 -> v3
* Add the MSI/MSI-x capability check
Do not add the device which supports MSI/MSI-x to the GSI sharing
group.
v1 -> v2
* Update the GSI raw data based on SBL
* Free the resources when gsi sharing violation occurs
* Move the MACRO PCI_BDF(b, d, f) to pci_core.h since passthrough.c
and gsi_sharing.c are both using it
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Edwin Zhai <edwin.zhai@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
130 lines
2.6 KiB
C
130 lines
2.6 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "pci_core.h"
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#define APL_MRB 1
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#ifdef APL_MRB
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struct gsi_dev gsi_dev_mapping_tables[] = {
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{"timer", 0},
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{"keyboard", 1},
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{"hpet0", 2},
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{"00:1b.0", 3},
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{"00:18.0", 4},
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{"00:18.1", 5},
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{"00:18.2", 6},
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{"00:18.3", 7},
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{"rtc", 8},
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{"acpi", 9},
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{"00:15.1", 13},
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{"gpio_ctlr", 14},
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{"00:15.0", 17},
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{"00:02.0", 19},
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{"00:12.0", 19},
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{"00:0f.0", 20},
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{"00:1f.1", 20},
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{"03:00.0", 20},
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{"00:03.0", 21},
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{"04:00.0", 21},
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{"00:00.1", 24},
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{"00:0e.0", 25},
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{"00:11.0", 26},
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{"00:16.0", 27},
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{"00:16.1", 28},
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{"00:16.2", 29},
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{"00:16.3", 30},
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{"00:17.0", 31},
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{"00:17.1", 32},
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{"00:17.2", 33},
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{"00:17.3", 34},
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{"00:19.0", 35},
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{"00:19.1", 36},
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{"00:19.2", 37},
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{"00:1c.0", 39},
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{"pmc_ipc", 40},
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{"00:1e.0", 42},
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{"gpio_pin_00", 50},
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{"gpio_pin_01", 51},
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{"gpio_pin_02", 52},
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{"gpio_pin_03", 53},
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{"gpio_pin_04", 54},
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{"gpio_pin_05", 55},
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{"gpio_pin_06", 56},
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{"gpio_pin_07", 57},
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{"gpio_pin_08", 58},
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{"gpio_pin_09", 59},
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{"gpio_pin_10", 60},
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{"gpio_pin_11", 61},
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{"gpio_pin_12", 62},
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{"gpio_pin_13", 63},
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{"gpio_pin_14", 64},
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{"gpio_pin_15", 65},
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{"gpio_pin_16", 66},
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{"gpio_pin_17", 67},
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{"gpio_pin_18", 68},
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{"gpio_pin_19", 69},
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{"gpio_pin_20", 70},
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{"gpio_pin_21", 71},
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{"gpio_pin_22", 72},
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{"gpio_pin_23", 73},
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{"gpio_pin_24", 74},
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{"gpio_pin_25", 75},
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{"gpio_pin_26", 76},
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{"gpio_pin_27", 77},
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{"gpio_pin_28", 78},
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{"gpio_pin_29", 79},
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{"gpio_pin_30", 80},
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{"gpio_pin_31", 81},
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{"gpio_pin_32", 82},
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{"gpio_pin_33", 83},
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{"gpio_pin_34", 84},
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{"gpio_pin_35", 85},
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{"gpio_pin_36", 86},
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{"gpio_pin_37", 87},
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{"gpio_pin_38", 88},
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{"gpio_pin_39", 89},
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{"gpio_pin_40", 90},
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{"gpio_pin_41", 91},
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{"gpio_pin_42", 92},
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{"gpio_pin_43", 93},
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{"gpio_pin_44", 94},
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{"gpio_pin_45", 95},
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{"gpio_pin_46", 96},
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{"gpio_pin_47", 97},
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{"gpio_pin_48", 98},
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{"gpio_pin_49", 99},
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{"gpio_pin_50", 100},
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{"gpio_pin_51", 101},
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{"gpio_pin_52", 102},
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{"gpio_pin_53", 103},
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{"gpio_pin_54", 104},
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{"gpio_pin_55", 105},
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{"gpio_pin_56", 106},
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{"gpio_pin_57", 107},
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{"gpio_pin_58", 108},
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{"gpio_pin_59", 109},
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{"gpio_pin_60", 110},
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{"gpio_pin_61", 111},
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{"gpio_pin_62", 112},
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{"gpio_pin_63", 113},
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{"gpio_pin_64", 114},
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{"gpio_pin_65", 115},
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{"gpio_pin_66", 116},
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{"gpio_pin_67", 117},
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{"gpio_pin_68", 118},
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{"gpio_pin_69", 119},
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};
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#else
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/*
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* Assume there is no GSI sharing if no hardcoded info is provided in
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* gsi_sharing_tables.
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*/
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struct gsi_dev gsi_dev_mapping_tables[] = {};
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#endif
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int num_gsi_dev_mapping_tables = ARRAY_SIZE(gsi_dev_mapping_tables);
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