mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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29b1ebcd43
1G PCI hole is added just after 4G address which is used as the PCI high MMIO address space. Guest high memory is mapped from 5G address for both EPT and device model user space address. Guest e820 table and API vm_map_gpa are updated accordingly. Tracked-On: #2577 Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Yu Wang <yu1.wang@intel.com>
83 lines
3.0 KiB
C
83 lines
3.0 KiB
C
/*-
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _CORE_SW_LOAD_
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#define _CORE_SW_LOAD_
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#define STR_LEN 1024
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/* E820 memory types */
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#define E820_TYPE_RAM 1 /* EFI 1, 2, 3, 4, 5, 6, 7 */
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/* EFI 0, 11, 12, 13 (everything not used elsewhere) */
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#define E820_TYPE_RESERVED 2
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#define E820_TYPE_ACPI_RECLAIM 3 /* EFI 9 */
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#define E820_TYPE_ACPI_NVS 4 /* EFI 10 */
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#define E820_TYPE_UNUSABLE 5 /* EFI 8 */
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#define NUM_E820_ENTRIES 7
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#define LOWRAM_E820_ENTRIES 2
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#define HIGHRAM_E820_ENTRIES 6
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/* Defines a single entry in an E820 memory map. */
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struct e820_entry {
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/** The base address of the memory range. */
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uint64_t baseaddr;
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/** The length of the memory range. */
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uint64_t length;
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/** The type of memory region. */
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uint32_t type;
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} __attribute__((packed));
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extern const struct e820_entry e820_default_entries[NUM_E820_ENTRIES];
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extern int with_bootargs;
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size_t ovmf_image_size(void);
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int acrn_parse_kernel(char *arg);
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int acrn_parse_ramdisk(char *arg);
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int acrn_parse_bootargs(char *arg);
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int acrn_parse_gvtargs(char *arg);
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int acrn_parse_vsbl(char *arg);
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int acrn_parse_ovmf(char *arg);
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int acrn_parse_elf(char *arg);
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int acrn_parse_guest_part_info(char *arg);
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char *get_bootargs(void);
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void vsbl_set_bdf(int bnum, int snum, int fnum);
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int check_image(char *path, size_t size_limit, size_t *size);
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uint32_t acrn_create_e820_table(struct vmctx *ctx, struct e820_entry *e820);
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int add_e820_entry(struct e820_entry *e820, int len, uint64_t start,
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uint64_t size, uint32_t type);
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int acrn_sw_load_bzimage(struct vmctx *ctx);
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int acrn_sw_load_elf(struct vmctx *ctx);
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int acrn_sw_load_vsbl(struct vmctx *ctx);
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int acrn_sw_load_ovmf(struct vmctx *ctx);
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int acrn_sw_load(struct vmctx *ctx);
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#endif
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