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https://github.com/projectacrn/acrn-hypervisor.git
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555a03db99
Currently the Px Cx supported SoCs which listed in cpu_state_tbl.c is limited, and it is not a wise option to build a huge state table data base to support Px/Cx for other SoCs. This patch give a alternative solution that build a board specific cpu state table in board.c which could be auto-generated by offline tool, then the CPU Px/Cx of customer board could be enabled; Hypervisor will search the cpu state table in cpu_state_tbl[] first, if not found then go check board_cpu_state_tbl. If no matched cpu state table is found then Px/Cx will not be supported; Tracked-On: #3477 Signed-off-by: Victor Sun <victor.sun@intel.com>
32 lines
615 B
C
32 lines
615 B
C
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <board.h>
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#include <msr.h>
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struct platform_clos_info platform_clos_array[4] = {
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{
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.clos_mask = 0xff,
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.msr_index = MSR_IA32_L2_MASK_0,
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},
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{
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.clos_mask = 0xff,
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.msr_index = MSR_IA32_L2_MASK_1,
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},
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{
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.clos_mask = 0xff,
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.msr_index = MSR_IA32_L2_MASK_2,
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},
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{
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.clos_mask = 0xff,
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.msr_index = MSR_IA32_L2_MASK_3,
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},
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};
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uint16_t platform_clos_num = (uint16_t)(sizeof(platform_clos_array)/sizeof(struct platform_clos_info));
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const struct cpu_state_table board_cpu_state_tbl;
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