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3cf1daa480
The vbar info which hard-coded in scenarios/logical_partition/pt_dev.c is board specific actually, so move these information to arch/x86/configs/$(CONFIG_BOARD)/pci_devices.h. Please be aware that the memory range of vBAR should exactly match with the e820 layout of VM. Tracked-On: #3214 Signed-off-by: Victor Sun <victor.sun@intel.com>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm_config.h>
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#include <pci_devices.h>
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/* The vbar_base info of pt devices is included in device MACROs which defined in
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* arch/x86/configs/$(CONFIG_BOARD)/pci_devices.h.
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* The memory range of vBAR should exactly match with the e820 layout of VM.
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*/
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struct acrn_vm_pci_ptdev_config vm0_pci_ptdevs[VM0_CONFIG_PCI_PTDEV_NUM] = {
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{
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.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
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HOST_BRIDGE
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},
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{
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
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VM0_STORAGE_CONTROLLER
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},
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{
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.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
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VM0_NETWORK_CONTROLLER
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},
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};
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struct acrn_vm_pci_ptdev_config vm1_pci_ptdevs[VM1_CONFIG_PCI_PTDEV_NUM] = {
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{
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.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
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HOST_BRIDGE
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},
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{
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.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
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VM1_STORAGE_CONTROLLER
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},
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#if defined(VM1_NETWORK_CONTROLLER)
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{
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.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
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VM1_NETWORK_CONTROLLER
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},
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#endif
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};
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