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6435259692
To avoid information leakage, we need to ensure that the device is
inaccessble when it does not exist.
For SR-IOV disabled VF device, we have the following operations.
1. The configuration space accessing will get 0xFFFFFFFF as a
return value after set the device state to zombie.
2. The BAR MMIO EPT mapping are removed, the accesssing causes
EPT violation.
3. The device will be detached from IOMMU.
4. The IRQ pin and vector are released.
Tracked-On: #4433
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
131 lines
4.3 KiB
C
131 lines
4.3 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef VPCI_PRIV_H_
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#define VPCI_PRIV_H_
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#include <pci.h>
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static inline bool in_range(uint32_t value, uint32_t lower, uint32_t len)
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{
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return ((value >= lower) && (value < (lower + len)));
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}
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/**
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* @pre vdev != NULL
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*/
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static inline bool has_msix_cap(const struct pci_vdev *vdev)
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{
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return (vdev->msix.capoff != 0U);
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}
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/**
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* @pre vdev != NULL
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*/
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static inline bool msixcap_access(const struct pci_vdev *vdev, uint32_t offset)
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{
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return (has_msix_cap(vdev) && in_range(offset, vdev->msix.capoff, vdev->msix.caplen));
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}
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/*
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* @pre vdev != NULL
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*/
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static inline bool has_sriov_cap(const struct pci_vdev *vdev)
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{
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return (vdev->sriov.capoff != 0U);
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}
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/*
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* @pre vdev != NULL
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*/
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static inline bool sriovcap_access(const struct pci_vdev *vdev, uint32_t offset)
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{
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return (has_sriov_cap(vdev) && in_range(offset, vdev->sriov.capoff, vdev->sriov.caplen));
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}
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/**
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* @pre vdev != NULL
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*/
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static inline bool vbar_access(const struct pci_vdev *vdev, uint32_t offset)
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{
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return is_bar_offset(vdev->nr_bars, offset);
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}
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/**
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* @pre vdev != NULL
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*/
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static inline bool cfg_header_access(uint32_t offset)
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{
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return (offset < PCI_CFG_HEADER_LENGTH);
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}
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/**
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* @pre vdev != NULL
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*/
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static inline bool has_msi_cap(const struct pci_vdev *vdev)
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{
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return (vdev->msi.capoff != 0U);
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}
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/**
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* @pre vdev != NULL
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*/
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static inline bool msicap_access(const struct pci_vdev *vdev, uint32_t offset)
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{
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return (has_msi_cap(vdev) && in_range(offset, vdev->msi.capoff, vdev->msi.caplen));
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}
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void init_vdev_pt(struct pci_vdev *vdev, bool is_pf_vdev);
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void deinit_vdev_pt(struct pci_vdev *vdev);
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void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val);
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void vdev_pt_map_msix(struct pci_vdev *vdev, bool hold_lock);
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void init_vmsi(struct pci_vdev *vdev);
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void read_vmsi_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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void write_vmsi_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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void deinit_vmsi(const struct pci_vdev *vdev);
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void init_vmsix(struct pci_vdev *vdev);
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int32_t vmsix_handle_table_mmio_access(struct io_request *io_req, void *handler_private_data);
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void read_vmsix_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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void write_vmsix_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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void deinit_vmsix(const struct pci_vdev *vdev);
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void init_vsriov(struct pci_vdev *vdev);
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void read_sriov_cap_reg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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void write_sriov_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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uint32_t sriov_bar_offset(const struct pci_vdev *vdev, uint32_t bar_idx);
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uint32_t pci_vdev_read_vcfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes);
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void pci_vdev_write_vcfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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uint32_t pci_vdev_read_vbar(const struct pci_vdev *vdev, uint32_t idx);
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void pci_vdev_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val);
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#endif /* VPCI_PRIV_H_ */
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