mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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b4a23e6c13
RTVM is enforced to use 4KB pages to mitigate CVE-2018-12207 and performance jitter, which may be introduced by splitting large page into 4KB pages on demand. It works fine in previous hardware platform where the size of address space for the RTVM is relatively small. However, this is a problem when the platforms support 64 bits high MMIO space, which could be super large and therefore consumes large # of EPT page table pages. This patch optimize it by using large page for purely data pages, such as MMIO spaces, even for the RTVM. Signed-off-by: Li Fei1 <fei1.li@intel.com> Tracked-On: #5788
86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PAGE_H
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#define PAGE_H
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#include <spinlock.h>
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#include <board_info.h>
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#define PAGE_SHIFT 12U
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#define PAGE_SIZE (1U << PAGE_SHIFT)
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#define PAGE_MASK 0xFFFFFFFFFFFFF000UL
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#define MAXIMUM_PA_WIDTH 39U /* maximum physical-address width */
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/* size of the low MMIO address space: 2GB */
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#define PLATFORM_LO_MMIO_SIZE 0x80000000UL
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/* size of the high MMIO address space: 1GB */
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#define PLATFORM_HI_MMIO_SIZE 0x40000000UL
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#define PML4_PAGE_NUM(size) 1UL
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#define PDPT_PAGE_NUM(size) (((size) + PML4E_SIZE - 1UL) >> PML4E_SHIFT)
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#define PD_PAGE_NUM(size) (((size) + PDPTE_SIZE - 1UL) >> PDPTE_SHIFT)
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#define PT_PAGE_NUM(size) (((size) + PDE_SIZE - 1UL) >> PDE_SHIFT)
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/**
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* @brief Page tables level in IA32 paging mode
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*/
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enum _page_table_level {
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/**
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* @brief The PML4 level in the page tables
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*/
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IA32E_PML4 = 0,
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/**
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* @brief The Page-Directory-Pointer-Table level in the page tables
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*/
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IA32E_PDPT = 1,
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/**
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* @brief The Page-Directory level in the page tables
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*/
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IA32E_PD = 2,
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/**
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* @brief The Page-Table level in the page tables
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*/
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IA32E_PT = 3,
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};
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struct acrn_vm;
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struct page {
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uint8_t contents[PAGE_SIZE];
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} __aligned(PAGE_SIZE);
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struct page_pool {
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struct page *start_page;
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spinlock_t lock;
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uint64_t bitmap_size;
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uint64_t *bitmap;
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uint64_t last_hint_id;
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struct page *dummy_page;
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};
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struct memory_ops {
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struct page_pool *pool;
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bool (*large_page_support)(enum _page_table_level level, uint64_t prot);
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uint64_t (*get_default_access_right)(void);
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uint64_t (*pgentry_present)(uint64_t pte);
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void (*clflush_pagewalk)(const void *p);
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void (*tweak_exe_right)(uint64_t *entry);
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void (*recover_exe_right)(uint64_t *entry);
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};
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extern const struct memory_ops ppt_mem_ops;
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void init_ept_mem_ops(struct memory_ops *mem_ops, uint16_t vm_id);
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struct page *alloc_page(struct page_pool *pool);
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void free_page(struct page_pool *pool, struct page *page);
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void *get_reserve_sworld_memory_base(void);
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void reserve_buffer_for_ept_pages(void);
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#endif /* PAGE_H */
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