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77ae989379
Initialize vCBM MSRs Initialize vCLOSID MSR Add some vCAT functions: Retrieve max_vcbm and max_pcbm Check if vCAT is configured or not for the VM Map vclosid to pclosid write_vclosid: vCLOSID MSR write handler write_vcbm: vCBM MSR write handler Tracked-On: #5917 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RDT_H
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#define RDT_H
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enum {
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RDT_RESOURCE_L3,
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RDT_RESOURCE_L2,
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RDT_RESOURCE_MBA,
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/* Must be the last */
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RDT_NUM_RESOURCES,
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};
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#define RDT_RESID_L3 1U
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#define RDT_RESID_L2 2U
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#define RDT_RESID_MBA 3U
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extern const uint16_t hv_clos;
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/* The intel Resource Director Tech(RDT) based Allocation Tech support */
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struct rdt_info {
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union {
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struct {
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uint32_t bitmask; /* A bitmask where each set bit indicates the corresponding cache way
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may be used by other entities in the platform (e.g. GPU) */
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uint16_t cbm_len; /* Length of Cache mask in bits */
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bool is_cdp_enabled; /* True if support CDP */
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uint32_t msr_qos_cfg; /* MSR addr to IA32_L3/L2_QOS_CFG */
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} cache;
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struct rdt_membw {
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uint16_t mba_max; /* Max MBA delay throttling value supported */
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bool delay_linear; /* True if memory B/W delay is in linear scale */
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} membw;
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} res;
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uint16_t num_closids; /* Number of CLOSIDs available, 0 indicates resource is not supported.*/
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uint32_t res_id;
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uint32_t msr_base; /* MSR base to program clos value */
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struct platform_clos_info *platform_clos_array; /* user configured mask and MSR info for each CLOS*/
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};
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void init_rdt_info(void);
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void setup_clos(uint16_t pcpu_id);
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uint64_t clos2pqr_msr(uint16_t clos);
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bool is_platform_rdt_capable(void);
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const struct rdt_info *get_rdt_res_cap_info(int res);
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#endif /* RDT_H */
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