Jian Jun Chen 22a302599a hv: tlfs: fix the incorrect vLAPIC freq MSR ...

When LAPIC timer is working in oneshot or periodic mode, OS uses
initial counter register/current counter register to program
a timer. Both initial counter and current counter depend on the
LAPIC frequency. ACRN emulated vLAPIC timer based on the TSC.
vLAPIC freq is the same as TSC freq.

Tracked-On: #7876
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>

2022-07-26 05:53:19 +08:00

..

assign.c

Update copyright year range in code headers

2022-07-15 11:48:35 +08:00

ept.c

Update copyright year range in code headers

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guest_memory.c

Update copyright year range in code headers

2022-07-15 11:48:35 +08:00

hyperv.c

hv: tlfs: fix the incorrect vLAPIC freq MSR

2022-07-26 05:53:19 +08:00

instr_emul.c

Update copyright year range in code headers

2022-07-15 11:48:35 +08:00

lock_instr_emul.c

Update copyright year range in code headers

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nested.c

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optee.c

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pm.c

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trusty.c

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ucode.c

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vcat.c

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vcpu.c

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vcpuid.c

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ve820.c

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vept.c

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virq.c

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virtual_cr.c

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vlapic_priv.h

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vlapic.c

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vm_reset.c

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vm.c

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vmcall.c

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vmcs.c

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vmexit.c

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vmsr.c

hv: tlfs: add tlfs TSC freq MSR support for WaaG

2022-07-18 16:15:29 +08:00

vmtrr.c

Update copyright year range in code headers

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vmx_asm.S

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vmx_io.c

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