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The current code would write 'BAR address & size_maks' into PCIe virtual BAR before updating the virtual BAR's base address when guest writing a PCIe device's BAR. If the size of a PCIe device's BAR is larger than 4G, the low 32 bits size_mask for this 64 bits BAR is zero. When ACRN updating the virtual BAR's base address, the low 32 bits sizing information would be lost. This patch saves whether a BAR writing is sizing or not before updating the virtual BAR's base address. Tracked-On: #8267 Signed-off-by: Fei Li <fei1.li@intel.com> |
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ivshmem.c | ||
pci_pt.c | ||
vdev.c | ||
vhostbridge.c | ||
vmcs9900.c | ||
vmsi.c | ||
vmsix_on_msi.c | ||
vmsix.c | ||
vpci_bridge.c | ||
vpci_priv.h | ||
vpci.c | ||
vroot_port.c | ||
vsriov.c |