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https://github.com/projectacrn/acrn-hypervisor.git
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023122c1cc
currently, pass-thru devices are managed by per-vm's remapping entries which is virtual based: - MSI entry is identified by virt_bdf+msix_index - INTx entry is identified by virt_pin+vpin_src it works but it's not a good design for physical resource management, for example a physical IOAPIC pin could belong to different vm's INTx entries, the Device Model then must make sure there is no resource conflict from application's level. This patch change the design from virtual to physical based: - MSI entry is identified by phys_bdf+msix_index - INTx entry is identified by phys_pin The physical resource is directly managed in hypervisor, a miss adding entry will be found by hypervisor and return error message with failure. Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Xu, Anthony <anthony.xu@intel.com>
60 lines
2.4 KiB
C
60 lines
2.4 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef IOAPIC_H
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#define IOAPIC_H
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/* IOAPIC_MAX_LINES is architecturally defined.
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* The usable RTEs may be a subset of the total on a per IO APIC basis.
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*/
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#define IOAPIC_MAX_LINES 120
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#define NR_LEGACY_IRQ 16
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#define NR_LEGACY_PIN NR_LEGACY_IRQ
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#define NR_MAX_GSI (NR_IOAPICS*IOAPIC_MAX_LINES)
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#define GSI_MASK_IRQ(irq) irq_gsi_mask_unmask((irq), true)
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#define GSI_UNMASK_IRQ(irq) irq_gsi_mask_unmask((irq), false)
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#define GSI_SET_RTE(irq, rte) ioapic_set_rte((irq), (rte))
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void setup_ioapic_irq(void);
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int get_ioapic_info(char *str, int str_max_len);
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bool irq_is_gsi(int irq);
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int irq_gsi_num(void);
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int irq_to_pin(int irq);
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int pin_to_irq(int pin);
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void irq_gsi_mask_unmask(int irq, bool mask);
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void ioapic_set_rte(int irq, uint64_t rte);
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void ioapic_get_rte(int irq, uint64_t *rte);
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extern uint16_t legacy_irq_to_pin[];
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extern uint16_t pic_ioapic_pin_map[];
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#endif /* IOAPIC_H */
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