mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-08-16 15:21:48 +00:00
V4: - If pci device is not found in the PCI mapping table, just return without throwing any error message - Added NULL pointer checking when calling cfgread/cfgwrite ops - Moved error checking code to cfgread/cfgwrite ops V3: - Do not use ASSERT - Call the cfg read/write ops defined in the vm description V2: - Fixed MISRA violations Reviewed-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
170 lines
4.5 KiB
C
170 lines
4.5 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <hypervisor.h>
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#include <hv_lib.h>
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#include <acrn_common.h>
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#include <hv_arch.h>
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#include <hv_debug.h>
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#include "pci_priv.h"
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static bool is_cfg_addr(uint16_t addr)
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{
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return (addr >= PCI_CONFIG_ADDR) && (addr < (PCI_CONFIG_ADDR + 4));
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}
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static bool is_cfg_data(uint16_t addr)
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{
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return (addr >= PCI_CONFIG_DATA) && (addr < (PCI_CONFIG_DATA + 4));
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}
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static void pci_cfg_clear_cache(struct pci_addr_info *pi)
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{
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pi->cached_bdf = 0xffffU;
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pi->cached_reg = 0U;
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pi->cached_enable = 0U;
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}
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static uint32_t pci_cfg_io_read(__unused struct vm_io_handler *hdlr,
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struct vm *vm, uint16_t addr, size_t bytes)
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{
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uint32_t val = 0xffffffffU;
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struct vpci *vpci = &vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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if (is_cfg_addr(addr)) {
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/* TODO: handling the non 4 bytes access */
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if (bytes == 4U) {
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val = (PCI_BUS(pi->cached_bdf) << 16)
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| (PCI_SLOT(pi->cached_bdf) << 11)
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| (PCI_FUNC(pi->cached_bdf) << 8)
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| pi->cached_reg;
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if (pi->cached_enable) {
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val |= PCI_CFG_ENABLE;
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}
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}
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} else if (is_cfg_data(addr)) {
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if (pi->cached_enable) {
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uint16_t offset = addr - 0xcfc;
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pci_vdev_cfg_handler(&vm->vpci, 1U, pi->cached_bdf,
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pi->cached_reg + offset, bytes, &val);
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pci_cfg_clear_cache(pi);
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}
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} else {
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val = 0xffffffffU;
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}
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return val;
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}
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static void pci_cfg_io_write(__unused struct vm_io_handler *hdlr,
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struct vm *vm, uint16_t addr, size_t bytes, uint32_t val)
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{
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struct vpci *vpci = &vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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if (is_cfg_addr(addr)) {
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/* TODO: handling the non 4 bytes access */
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if (bytes == 4U) {
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pi->cached_bdf = PCI_BDF(
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((val >> 16) & PCI_BUSMAX),
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((val >> 11) & PCI_SLOTMAX),
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((val >> 8) & PCI_FUNCMAX));
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pi->cached_reg = val & PCI_REGMAX;
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pi->cached_enable =
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(val & PCI_CFG_ENABLE) == PCI_CFG_ENABLE;
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}
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} else if (is_cfg_data(addr)) {
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if (pi->cached_enable) {
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uint16_t offset = addr - 0xcfc;
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pci_vdev_cfg_handler(&vm->vpci, 0U, pi->cached_bdf,
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pi->cached_reg + offset, bytes, &val);
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pci_cfg_clear_cache(pi);
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}
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} else {
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pr_err("Not PCI cfg data/addr port access!");
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}
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}
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void vpci_init(struct vm *vm)
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{
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struct vpci *vpci = &vm->vpci;
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struct vpci_vdev_array *vdev_array;
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struct pci_vdev *vdev;
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int i;
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int ret;
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struct vm_io_range pci_cfg_range = {.flags = IO_ATTR_RW,
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.base = PCI_CONFIG_ADDR, .len = 8U};
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vpci->vm = vm;
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vdev_array = vm->vm_desc->vpci_vdev_array;
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for (i = 0; i < vdev_array->num_pci_vdev; i++) {
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vdev = &vdev_array->vpci_vdev_list[i];
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vdev->vpci = vpci;
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if ((vdev->ops != NULL) && (vdev->ops->init != NULL)) {
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ret = vdev->ops->init(vdev);
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if (ret) {
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pr_err("vdev->ops->init failed!");
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}
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}
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}
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register_io_emulation_handler(vm, &pci_cfg_range,
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&pci_cfg_io_read, &pci_cfg_io_write);
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}
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void vpci_cleanup(struct vm *vm)
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{
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struct vpci_vdev_array *vdev_array;
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struct pci_vdev *vdev;
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int i;
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int ret;
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vdev_array = vm->vm_desc->vpci_vdev_array;
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for (i = 0; i < vdev_array->num_pci_vdev; i++) {
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vdev = &vdev_array->vpci_vdev_list[i];
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if ((vdev->ops != NULL) && (vdev->ops->deinit != NULL)) {
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ret = vdev->ops->deinit(vdev);
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if (ret) {
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pr_err("vdev->ops->deinit failed!");
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}
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}
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}
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}
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