mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2026-06-06 17:21:22 +00:00
009d835bba
As the blkid info contains 'UUID' information, which easy to lead to
confuse with the vm 'UUID'. So refine the format for block device.
v1-v2:
1). align the style in BLOCK_DEVICE_INFO tag
2). add 'mmcblk1p3' in BLOCK_DEVICE_INFO tag
v2-v3:
1). correct the commit message.
2). refine the api of handle_block_dev
Tracked-On: #3754
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
300 lines
14 KiB
XML
300 lines
14 KiB
XML
<acrn-config board="apl-up2">
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<BIOS_INFO>
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BIOS Information
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Vendor: American Megatrends Inc.
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Version: UPA1AM46
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Release Date: 08/14/2019
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BIOS Revision: 5.12
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</BIOS_INFO>
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<BASE_BOARD_INFO>
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Base Board Information
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Manufacturer: AAEON
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Product Name: UP-APL01
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Version: V0.4
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</BASE_BOARD_INFO>
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<PCI_DEVICE>
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00:00.0 Host bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Host Bridge (rev 0b)
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00:02.0 VGA compatible controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Integrated Graphics Controller (rev 0b)
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Region 0: Memory at 90000000 (64-bit, non-prefetchable) [size=16M]
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Region 2: Memory at 80000000 (64-bit, prefetchable) [size=256M]
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00:0e.0 Multimedia audio controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Audio Cluster (rev 0b)
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Region 0: Memory at 91510000 (64-bit, non-prefetchable) [size=16K]
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Region 4: Memory at 91200000 (64-bit, non-prefetchable) [size=1M]
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00:0f.0 Communication controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Trusted Execution Engine (rev 0b)
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Region 0: Memory at 9153c000 (64-bit, non-prefetchable) [size=4K]
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00:12.0 SATA controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SATA AHCI Controller (rev 0b)
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Region 0: Memory at 91514000 (32-bit, non-prefetchable) [size=8K]
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Region 1: Memory at 91539000 (32-bit, non-prefetchable) [size=256]
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Region 5: Memory at 91538000 (32-bit, non-prefetchable) [size=2K]
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00:13.0 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port A #1 (rev fb)
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00:13.1 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port A #2 (rev fb)
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00:13.2 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port A #3 (rev fb)
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00:13.3 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port A #4 (rev fb)
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00:14.0 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1 (rev fb)
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00:14.1 PCI bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #2 (rev fb)
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00:15.0 USB controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series USB xHCI (rev 0b)
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Region 0: Memory at 91500000 (64-bit, non-prefetchable) [size=64K]
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00:15.1 USB controller: Intel Corporation Device 5aaa (rev 0b)
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Region 0: Memory at 91000000 (64-bit, non-prefetchable) [disabled] [size=2M]
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Region 2: Memory at 91537000 (64-bit, non-prefetchable) [disabled] [size=4K]
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00:16.0 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #1 (rev 0b)
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Region 0: Memory at 91536000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91535000 (64-bit, non-prefetchable) [size=4K]
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00:16.1 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #2 (rev 0b)
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Region 0: Memory at 91534000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91533000 (64-bit, non-prefetchable) [size=4K]
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00:16.2 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #3 (rev 0b)
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Region 0: Memory at 91532000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91531000 (64-bit, non-prefetchable) [size=4K]
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00:16.3 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #4 (rev 0b)
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Region 0: Memory at 91530000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 9152f000 (64-bit, non-prefetchable) [size=4K]
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00:17.0 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #5 (rev 0b)
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Region 0: Memory at 9152e000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 9152d000 (64-bit, non-prefetchable) [size=4K]
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00:17.1 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #6 (rev 0b)
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Region 0: Memory at 9152c000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 9152b000 (64-bit, non-prefetchable) [size=4K]
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00:17.2 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #7 (rev 0b)
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Region 0: Memory at 9152a000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91529000 (64-bit, non-prefetchable) [size=4K]
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00:17.3 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series I2C Controller #8 (rev 0b)
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Region 0: Memory at 91528000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91527000 (64-bit, non-prefetchable) [size=4K]
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00:18.0 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series HSUART Controller #1 (rev 0b)
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Region 0: Memory at 91526000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91525000 (64-bit, non-prefetchable) [size=4K]
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00:18.1 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series HSUART Controller #2 (rev 0b)
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Region 0: Memory at 91524000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91523000 (64-bit, non-prefetchable) [size=4K]
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00:19.0 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SPI Controller #1 (rev 0b)
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Region 0: Memory at 91522000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91521000 (64-bit, non-prefetchable) [size=4K]
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00:19.1 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SPI Controller #2 (rev 0b)
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Region 0: Memory at 91520000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 9151f000 (64-bit, non-prefetchable) [size=4K]
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00:19.2 Signal processing controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SPI Controller #3 (rev 0b)
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Region 0: Memory at 9151e000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 9151d000 (64-bit, non-prefetchable) [size=4K]
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00:1a.0 Serial bus controller [0c80]: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series PWM Pin Controller (rev 0b)
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Region 0: Memory at 9151c000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 9151b000 (64-bit, non-prefetchable) [size=4K]
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00:1c.0 SD Host controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series eMMC Controller (rev 0b)
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Region 0: Memory at 9151a000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91519000 (64-bit, non-prefetchable) [size=4K]
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00:1e.0 SD Host controller: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SDIO Controller (rev 0b)
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Region 0: Memory at 91518000 (64-bit, non-prefetchable) [size=4K]
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Region 2: Memory at 91517000 (64-bit, non-prefetchable) [size=4K]
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00:1f.0 ISA bridge: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series Low Pin Count Interface (rev 0b)
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00:1f.1 SMBus: Intel Corporation Celeron N3350/Pentium N4200/Atom E3900 Series SMBus Controller (rev 0b)
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Region 0: Memory at 91516000 (64-bit, non-prefetchable) [size=256]
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02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 0c)
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Region 2: Memory at 91404000 (64-bit, non-prefetchable) [size=4K]
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Region 4: Memory at 91400000 (64-bit, prefetchable) [size=16K]
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03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 0c)
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Region 2: Memory at 91304000 (64-bit, non-prefetchable) [size=4K]
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Region 4: Memory at 91300000 (64-bit, prefetchable) [size=16K]
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</PCI_DEVICE>
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<PCI_VID_PID>
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00:00.0 0600: 8086:5af0 (rev 0b)
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00:02.0 0300: 8086:5a84 (rev 0b)
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00:0e.0 0401: 8086:5a98 (rev 0b)
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00:0f.0 0780: 8086:5a9a (rev 0b)
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00:12.0 0106: 8086:5ae3 (rev 0b)
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00:13.0 0604: 8086:5ad8 (rev fb)
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00:13.1 0604: 8086:5ad9 (rev fb)
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00:13.2 0604: 8086:5ada (rev fb)
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00:13.3 0604: 8086:5adb (rev fb)
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00:14.0 0604: 8086:5ad6 (rev fb)
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00:14.1 0604: 8086:5ad7 (rev fb)
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00:15.0 0c03: 8086:5aa8 (rev 0b)
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00:15.1 0c03: 8086:5aaa (rev 0b)
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00:16.0 1180: 8086:5aac (rev 0b)
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00:16.1 1180: 8086:5aae (rev 0b)
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00:16.2 1180: 8086:5ab0 (rev 0b)
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00:16.3 1180: 8086:5ab2 (rev 0b)
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00:17.0 1180: 8086:5ab4 (rev 0b)
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00:17.1 1180: 8086:5ab6 (rev 0b)
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00:17.2 1180: 8086:5ab8 (rev 0b)
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00:17.3 1180: 8086:5aba (rev 0b)
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00:18.0 1180: 8086:5abc (rev 0b)
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00:18.1 1180: 8086:5abe (rev 0b)
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00:19.0 1180: 8086:5ac2 (rev 0b)
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00:19.1 1180: 8086:5ac4 (rev 0b)
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00:19.2 1180: 8086:5ac6 (rev 0b)
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00:1a.0 0c80: 8086:5ac8 (rev 0b)
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00:1c.0 0805: 8086:5acc (rev 0b)
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00:1e.0 0805: 8086:5ad0 (rev 0b)
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00:1f.0 0601: 8086:5ae8 (rev 0b)
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00:1f.1 0c05: 8086:5ad4 (rev 0b)
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02:00.0 0200: 10ec:8168 (rev 0c)
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03:00.0 0200: 10ec:8168 (rev 0c)
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</PCI_VID_PID>
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<WAKE_VECTOR_INFO>
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#define WAKE_VECTOR_32 0x79CA108CUL
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#define WAKE_VECTOR_64 0x79CA1098UL
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</WAKE_VECTOR_INFO>
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<RESET_REGISTER_INFO>
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#define RESET_REGISTER_ADDRESS 0xCF9UL
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#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
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#define RESET_REGISTER_VALUE 0x6U
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</RESET_REGISTER_INFO>
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<PM_INFO>
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#define PM1A_EVT_SPACE_ID SPACE_SYSTEM_IO
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#define PM1A_EVT_BIT_WIDTH 0x20U
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#define PM1A_EVT_BIT_OFFSET 0x0U
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#define PM1A_EVT_ADDRESS 0x400UL
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#define PM1A_EVT_ACCESS_SIZE 0x2U
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#define PM1B_EVT_SPACE_ID SPACE_SYSTEM_IO
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#define PM1B_EVT_BIT_WIDTH 0x0U
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#define PM1B_EVT_BIT_OFFSET 0x0U
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#define PM1B_EVT_ADDRESS 0x0UL
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#define PM1B_EVT_ACCESS_SIZE 0x2U
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#define PM1A_CNT_SPACE_ID SPACE_SYSTEM_IO
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#define PM1A_CNT_BIT_WIDTH 0x10U
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#define PM1A_CNT_BIT_OFFSET 0x0U
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#define PM1A_CNT_ADDRESS 0x404UL
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#define PM1A_CNT_ACCESS_SIZE 0x2U
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#define PM1B_CNT_SPACE_ID SPACE_SYSTEM_IO
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#define PM1B_CNT_BIT_WIDTH 0x0U
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#define PM1B_CNT_BIT_OFFSET 0x0U
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#define PM1B_CNT_ADDRESS 0x0UL
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#define PM1B_CNT_ACCESS_SIZE 0x2U
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</PM_INFO>
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<S3_INFO>
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#define S3_PKG_VAL_PM1A 0x5U
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#define S3_PKG_VAL_PM1B 0U
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#define S3_PKG_RESERVED 0x0U
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</S3_INFO>
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<S5_INFO>
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#define S5_PKG_VAL_PM1A 0x7U
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#define S5_PKG_VAL_PM1B 0U
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#define S5_PKG_RESERVED 0x0U
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</S5_INFO>
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<DRHD_INFO>
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#define DRHD_COUNT 2U
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#define DRHD0_DEV_CNT 1U
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#define DRHD0_SEGMENT 0U
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#define DRHD0_FLAGS 0U
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#define DRHD0_REG_BASE 0xFED64000UL
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#define DRHD0_IGNORE false
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#define DRHD0_DEVSCOPE0_BUS 0x0U
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#define DRHD0_DEVSCOPE0_PATH 0x10U
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#define DRHD0_DEVSCOPE1_BUS 0x0U
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#define DRHD0_DEVSCOPE1_PATH 0x0U
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#define DRHD0_DEVSCOPE2_BUS 0x0U
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#define DRHD0_DEVSCOPE2_PATH 0x0U
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#define DRHD0_DEVSCOPE3_BUS 0x0U
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#define DRHD0_DEVSCOPE3_PATH 0x0U
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#define DRHD1_DEV_CNT 2U
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#define DRHD1_SEGMENT 0U
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#define DRHD1_FLAGS 1U
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#define DRHD1_REG_BASE 0xFED65000UL
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#define DRHD1_IGNORE false
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#define DRHD1_DEVSCOPE0_BUS 0xfaU
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#define DRHD1_DEVSCOPE0_PATH 0xf8U
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#define DRHD1_DEVSCOPE1_BUS 0x0U
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#define DRHD1_DEVSCOPE1_PATH 0xffU
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#define DRHD1_DEVSCOPE2_BUS 0x0U
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#define DRHD1_DEVSCOPE2_PATH 0x0U
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#define DRHD1_DEVSCOPE3_BUS 0x0U
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#define DRHD1_DEVSCOPE3_PATH 0x0U
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#define DRHD1_IOAPIC_ID 1U
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#define DRHD2_DEV_CNT 0U
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#define DRHD2_SEGMENT 0U
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#define DRHD2_FLAGS 0U
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#define DRHD2_REG_BASE 0x00UL
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#define DRHD2_IGNORE false
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#define DRHD2_DEVSCOPE0_BUS 0x0U
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#define DRHD2_DEVSCOPE0_PATH 0x0U
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#define DRHD2_DEVSCOPE1_BUS 0x0U
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#define DRHD2_DEVSCOPE1_PATH 0x0U
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#define DRHD2_DEVSCOPE2_BUS 0x0U
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#define DRHD2_DEVSCOPE2_PATH 0x0U
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#define DRHD2_DEVSCOPE3_BUS 0x0U
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#define DRHD2_DEVSCOPE3_PATH 0x0U
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#define DRHD3_DEV_CNT 0U
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#define DRHD3_SEGMENT 0U
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#define DRHD3_FLAGS 0U
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#define DRHD3_REG_BASE 0x00UL
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#define DRHD3_IGNORE false
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#define DRHD3_DEVSCOPE0_BUS 0x0U
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#define DRHD3_DEVSCOPE0_PATH 0x0U
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#define DRHD3_DEVSCOPE1_BUS 0x0U
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#define DRHD3_DEVSCOPE1_PATH 0x0U
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#define DRHD3_DEVSCOPE2_BUS 0x0U
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#define DRHD3_DEVSCOPE2_PATH 0x0U
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#define DRHD3_DEVSCOPE3_BUS 0x0U
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#define DRHD3_DEVSCOPE3_PATH 0x0U
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</DRHD_INFO>
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<CPU_BRAND>
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"Intel(R) Pentium(R) CPU N4200 @ 1.10GHz"
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</CPU_BRAND>
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<CX_INFO>
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{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
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{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x415UL}, 0x02U, 0x32U, 0x00U}, /* C2 */
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{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x419UL}, 0x03U, 0x96U, 0x00U}, /* C3 */
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</CX_INFO>
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<PX_INFO>
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{0x44DUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001900UL, 0x001900UL}, /* P0 */
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{0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P1 */
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{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P2 */
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{0x384UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000900UL, 0x000900UL}, /* P3 */
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{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P4 */
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</PX_INFO>
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<CLOS_INFO>
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clos supported by cache:L2
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clos max:4
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</CLOS_INFO>
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<SYSTEM_RAM_INFO>
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00001000-0003efff : System RAM
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00040000-0009dfff : System RAM
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00100000-0fffffff : System RAM
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12151000-70884017 : System RAM
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70884018-70894057 : System RAM
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70894058-77b0afff : System RAM
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7a08b000-7a3f8fff : System RAM
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7a424000-7a964fff : System RAM
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7a967000-7affffff : System RAM
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100000000-27fffffff : System RAM
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</SYSTEM_RAM_INFO>
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<BLOCK_DEVICE_INFO>
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/dev/sda3: TYPE="ext4"
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/dev/mmcblk0p1: TYPE="ext4"
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/dev/mmcblk0p3: TYPE="ext4"
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</BLOCK_DEVICE_INFO>
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<TTYS_INFO>
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BDF:(00:18.0) seri:/dev/ttyS0 base:0x91526000 irq:4
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BDF:(00:18.1) seri:/dev/ttyS1 base:0x91524000 irq:5
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</TTYS_INFO>
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<AVAILABLE_IRQ_INFO>
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3, 6, 7, 10, 11, 12, 13, 15
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</AVAILABLE_IRQ_INFO>
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<TOTAL_MEM_INFO>
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8066364 kB
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</TOTAL_MEM_INFO>
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<CPU_PROCESSOR_INFO>
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0, 1, 2, 3
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</CPU_PROCESSOR_INFO>
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</acrn-config>
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