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090aaf4c34
Follow multi-arch design, implement the mandatory arch barrier functions declared in common barrier.h for risc-v support. Tracked-On: #8803 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Co-developed-by: Haoyu Tang <haoyu.tang@intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
29 lines
684 B
C
29 lines
684 B
C
/*
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* Copyright (C) 2023-2025 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef RISCV_LIB_BARRIER_H
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#define RISCV_LIB_BARRIER_H
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/* Synchronizes all read accesses to/from memory */
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static inline void arch_cpu_read_memory_barrier(void)
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{
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asm volatile ("fence r,r" : : : "memory");
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}
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static inline void arch_cpu_write_memory_barrier(void)
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{
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asm volatile ("fence w,w" : : : "memory");
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}
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/* Synchronizes all read and write accesses to/from memory */
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static inline void arch_cpu_memory_barrier(void)
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{
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asm volatile ("fence rw,rw" : : : "memory");
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}
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#endif /* RISCV_LIB_BARRIER_H */
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