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https://github.com/projectacrn/acrn-hypervisor.git
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0255e62798
After enabling vPCI in hypervisor for vm0, UOS may not able be launched successfully. Consider this scenario (take MSI-X for example): - DM makes hypercall to hypervisor to do MSI-X remapping on behalf of UOS guests. - After the hypercall, VHM module in SOS kernel updates the physical MSI-X table with the physical Message Data/Addr. - These MMIO write requests are intercepted by hypervisor, which will call ptdev_msix_remap() to do MSI-S remapping. It may fail due to 2 possible reasons: 1) wrong target VM because: hypervisor thinks it's a VM0 MSI-X device but they have been registered as UOS guests through HC_SET_PTDEV_INTR_INFO hypercall. 2) wrong ptdev_msi_info->vmsi_data because: The virtual MSI-X table is supposed to hold virtual Message data/addr but the SOS VHM writes the physical ones to it. This patch resolves these problems by ignoring the HC_VM_PCI_MSIX_REMAP hypercall, so virtual and physical Message Data are the same from SOS' perspective and it won't mess up the virtual PCI device in HV. Also in HC_SET_PTDEV_INTR_INFO handler, vpci updates the target VM when the PCI devices are assigned to different VMs. The UOS' MSI/MSI-X remapping is triggered by hypervisor when SOS (either DM or VHM) updates the Message Data/Addr. Tracked-On: #1568 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef VPCI_H_
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#define VPCI_H_
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#include <pci.h>
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struct pci_vdev;
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struct pci_vdev_ops {
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int (*init)(struct pci_vdev *vdev);
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int (*deinit)(struct pci_vdev *vdev);
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int (*cfgwrite)(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val);
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int (*cfgread)(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val);
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};
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struct pci_bar {
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uint64_t base;
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uint64_t size;
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enum pci_bar_type type;
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};
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struct msix_table_entry {
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uint64_t addr;
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uint32_t data;
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uint32_t vector_control;
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};
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struct pci_pdev {
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/* The bar info of the physical PCI device. */
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struct pci_bar bar[PCI_BAR_COUNT];
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/* The bus/device/function triple of the physical PCI device. */
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union pci_bdf bdf;
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};
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/* MSI capability structure */
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struct msi {
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uint32_t capoff;
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uint32_t caplen;
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};
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/* MSI-X capability structure */
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struct msix {
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struct msix_table_entry tables[CONFIG_MAX_MSIX_TABLE_NUM];
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uint64_t mmio_gpa;
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uint64_t mmio_hva;
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uint64_t mmio_size;
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uint64_t intercepted_gpa;
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uint64_t intercepted_size;
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uint32_t capoff;
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uint32_t caplen;
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uint32_t table_bar;
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uint32_t table_offset;
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uint32_t table_count;
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};
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union cfgdata {
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uint8_t data_8[PCI_REGMAX + 1U];
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uint16_t data_16[(PCI_REGMAX + 1U) >> 2U];
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uint32_t data_32[(PCI_REGMAX + 1U) >> 4U];
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};
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struct pci_vdev {
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#ifndef CONFIG_PARTITION_MODE
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#define MAX_VPCI_DEV_OPS 4U
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struct pci_vdev_ops ops[MAX_VPCI_DEV_OPS];
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uint32_t nr_ops;
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#else
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struct pci_vdev_ops *ops;
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#endif
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struct vpci *vpci;
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/* The bus/device/function triple of the virtual PCI device. */
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union pci_bdf vbdf;
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struct pci_pdev pdev;
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union cfgdata cfgdata;
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/* The bar info of the virtual PCI device. */
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struct pci_bar bar[PCI_BAR_COUNT];
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#ifndef CONFIG_PARTITION_MODE
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struct msi msi;
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struct msix msix;
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#endif
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};
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struct pci_addr_info {
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union pci_bdf cached_bdf;
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uint32_t cached_reg, cached_enable;
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};
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struct vpci_ops {
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int (*init)(struct vm *vm);
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void (*deinit)(struct vm *vm);
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void (*cfgread)(struct vpci *vpci, union pci_bdf vbdf, uint32_t offset,
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uint32_t bytes, uint32_t *val);
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void (*cfgwrite)(struct vpci *vpci, union pci_bdf vbdf, uint32_t offset,
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uint32_t bytes, uint32_t val);
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};
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struct vpci {
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struct vm *vm;
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struct pci_addr_info addr_info;
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struct vpci_ops *ops;
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};
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extern struct pci_vdev_ops pci_ops_vdev_hostbridge;
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extern struct pci_vdev_ops pci_ops_vdev_pt;
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void vpci_init(struct vm *vm);
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void vpci_cleanup(struct vm *vm);
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void vpci_set_ptdev_intr_info(struct vm *target_vm, uint16_t vbdf, uint16_t pbdf);
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void vpci_reset_ptdev_intr_info(struct vm *target_vm, uint16_t vbdf, uint16_t pbdf);
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#endif /* VPCI_H_ */
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