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052a58d87d
add wait_sync_change and arch_get_pcpu_num implementation for riscv. MAX_PCPU_NUM comes from board_info.h generated by config tool. v2->v3: remove riscv cpu.c include asm/cpu.h v1->v2: implement arch_get_num_available_cpus(); Tracked-On: #8801 signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: hangliu1 <hang1.liu@intel.com> Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Wang, Yu1 <yu1.wang@intel.com> Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
40 lines
889 B
C
40 lines
889 B
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#include <types.h>
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#include <lib/util.h>
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#include <debug/logmsg.h>
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#include <board_info.h>
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#define barrier() __asm__ __volatile__("fence": : :"memory")
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#define cpu_relax() barrier() /* TODO: replace with yield instruction */
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#define NR_CPUS MAX_PCPU_NUM
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static inline uint16_t get_pcpu_id(void)
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{
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/**
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* Dummy implementation.
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* Official implementations are to be provided in the platform initialization patchset (by Hang).
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*/
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return 0U;
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}
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/* Write CSR */
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#define cpu_csr_write(reg, csr_val) \
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({ \
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uint64_t val = (uint64_t)csr_val; \
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asm volatile (" csrw " STRINGIFY(reg) ", %0 \n\t" \
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:: "r"(val): "memory"); \
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})
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void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
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#endif /* RISCV_CPU_H */
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