Haiwei Li 5283c147ef hv: pci: Add guest cfg header access handling of type 1 device ... When guests resume form s3, an error occurs in guest: ``` pcieport 0000:00:1c.0: refused to change power state from D0 to D3hot ``` PCI bridge (type 1 device) will access configuration space header but now acrn is not supported. So add handling support. Tracked-On: #8623 Signed-off-by: Haiwei Li <haiwei.li@intel.com>		2024-06-27 11:26:09 +08:00
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ivshmem.c	hv: dm: refine create/destroy functions	2024-06-04 09:38:34 +08:00
pci_pt.c	hv: pci: restore bus and memory/IO info after reset	2024-06-27 11:26:09 +08:00
vdev.c	hv: vpci: clear vdev structure on device deassign	2024-06-04 09:38:34 +08:00
vhostbridge.c	Update copyright year range in code headers	2022-07-15 11:48:35 +08:00
vmcs9900.c	hv: dm: refine create/destroy functions	2024-06-04 09:38:34 +08:00
vmsi.c	Update copyright year range in code headers	2022-07-15 11:48:35 +08:00
vmsix_on_msi.c	Update copyright year range in code headers	2022-07-15 11:48:35 +08:00
vmsix.c	hv: vpci: fix pass-thru pcie device may access MSI-X BAR	2022-10-26 01:02:20 +08:00
vpci_bridge.c	Update copyright year range in code headers	2022-07-15 11:48:35 +08:00
vpci_mf_dev.c	HV: emulate dummy multi-function dev in Service VM	2023-09-11 16:13:16 +08:00
vpci_priv.h	hv: pci: restore bus and memory/IO info after reset	2024-06-27 11:26:09 +08:00
vpci.c	hv: pci: Add guest cfg header access handling of type 1 device	2024-06-27 11:26:09 +08:00
vroot_port.c	hv: dm: refine create/destroy functions	2024-06-04 09:38:34 +08:00
vsriov.c	Update copyright year range in code headers	2022-07-15 11:48:35 +08:00