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https://github.com/projectacrn/acrn-hypervisor.git
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f6bf0b809d
This patch implements risc-v specific timer codes. Basically, risc-v adapts to acrn timer framework with some specific behaviors. So far, it enables sstc support in h-mode. Tracked-On: #8792 Signed-off-by: Haicheng Li <haicheng.li@outlook.com> Co-developed-by: Yong Li <yong.li@intel.com> Signed-off-by: Yong Li <yong.li@intel.com> Co-developed-by: Yi Y Sun <yi.y.sun@intel.com> Signed-off-by: Yi Y Sun <yi.y.sun@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
24 lines
490 B
C
24 lines
490 B
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOFTIRQ_H
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#define SOFTIRQ_H
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#include <lib/types.h>
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#define SOFTIRQ_TIMER 0U
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#define SOFTIRQ_PTDEV 1U
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#define SOFTIRQ_THERMAL 2U
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#define NR_SOFTIRQS 3U
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typedef void (*softirq_handler)(uint16_t cpu_id);
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void init_softirq(void);
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void register_softirq(uint16_t nr, softirq_handler handler);
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void fire_softirq(uint16_t nr);
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void do_softirq(void);
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#endif /* SOFTIRQ_H */
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