Yan, Like 0d998d6ac6 hv: sync physical and virtual TSC_DEADLINE when msr interception enabled/disabled ...

Starting with TSC_DEADLINE msr interception disabled, the virtual TSC_DEADLINE msr is always 0.
When the interception is enabled, need to sync the physical TSC_DEADLINE value to virtual TSC_DEADLINE.

When the interception is disabled, there are 2 cases:
 - if the timer hasn't expired, sync virtual TSC_DEADLINE to physical TSC_DEADLINE, to make the guest read the same tsc_deadline
   as it writes. This may change when the timer actually trigger.
 - if the timer has expired, write 0 to the virtual TSC_DEADLINE.

Tracked-On: #4162
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

2019-12-02 16:10:50 +08:00

..

x86

hv: sync physical and virtual TSC_DEADLINE when msr interception enabled/disabled

2019-12-02 16:10:50 +08:00