Haicheng Li 0fc843de84 hv: riscv: irq: add misc IRQ-dependent helpers ...

Introduce cpu_csr_clear() and cpu_dead(), which are required by
the exception and interrupt handler implementations.

Tracked-On: #8813
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu  <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>

2025-09-29 14:01:00 +08:00

..

riscv/asm

hv: riscv: irq: add misc IRQ-dependent helpers

2025-09-29 14:01:00 +08:00

x86/asm

hv: multi-arch: move SP_BOTTOM_MAGIC to common/cpu.h

2025-09-23 11:30:38 +08:00