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07afbce7bb
Add RISC-V specific implementation of arch_get_random_value() that combines entropy from rdcycle and rdtime counters. This provides a portable solution since the Zkr entropy extension is optional in RVA23 profile. Tracked-On: #8834 Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Reviewed-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
40 lines
1.3 KiB
C
40 lines
1.3 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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/**
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* @brief Generate a random 64-bit value using RISC-V timing counters
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*
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* This function provides a portable random number generation mechanism for
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* RISC-V systems by combining entropy from hardware timing counters. Since
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* the Zkr (Entropy Source) extension is optional in RVA23 profile and not
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* universally available, this implementation uses standard timing counters
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* that are present in all RISC-V systems.
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*
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* The implementation combines two entropy sources:
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* - rdcycle: CPU cycle counter (high frequency, fast changing)
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* - rdtime: Real-time counter (lower frequency, slower changing)
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*
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* The time counter value is left-shifted by 13 bits before XORing with the
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* cycle counter. The shift value 13 is chosen to compensate for the frequency
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* difference between counters.
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*
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* @return uint64_t A 64-bit pseudo-random value
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*
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* @fixme TODO: Detect Zkr extension availability and use CSR_SEED (0x015)
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* when hardware entropy source is present for better randomness quality.
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*/
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uint64_t arch_get_random_value(void)
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{
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uint64_t cycle, time;
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asm volatile ("rdcycle %0" : "=r"(cycle));
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asm volatile ("rdtime %0" : "=r"(time));
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return cycle ^ (time << 13U);
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}
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