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13e99bc0b9
In spite of Table Size in MSI-X Message Control Register [Bits 10:0] masks as RO (Register bits are read-only and cannot be altered by software), In Spec PCIe 6.0, Chap 6.1.4.2 MSI-X Configuration "Depending upon system software policy, system software, device driver software, or each at different times or environments may configure a Function’s MSI-X Capability and table structures with suitable vectors." This patch just pass through MSI-X Control Register field to guest. Tracked-On: #7275 Signed-off-by: Fei Li <fei1.li@intel.com>