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d0665fe220
cache configuration. This patch creates a generic infrastructure for RDT resources instead of just L2 or L3 cache. This patch also fixes L3 CAT config overwrite by L2 in cases where both L2 and L3 CAT are supported. Tracked-On: #3715 Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
40 lines
1004 B
C
40 lines
1004 B
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RDT_H
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#define RDT_H
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enum {
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RDT_RESOURCE_L3,
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RDT_RESOURCE_L2,
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/* Must be the last */
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RDT_NUM_RESOURCES,
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};
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#define RDT_RESID_L3 1U
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#define RDT_RESID_L2 2U
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extern const uint16_t hv_clos;
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extern const uint16_t platform_clos_num;
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/* The intel Resource Director Tech(RDT) based Allocation Tech support */
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struct rdt_info {
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uint32_t bitmask; /* Shared CLOS bitmask used by other entities */
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uint16_t cbm_len; /* Length of Cache mask in bits */
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uint16_t clos_max; /* Maximum CLOS supported, 0 indicates resource is not supported.*/
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uint32_t res_id;
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uint32_t msr_base; /* MSR base to program clos mask*/
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struct platform_clos_info *platform_clos_array; /* user configured mask and MSR info for each CLOS*/
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};
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int32_t init_rdt_cap_info(void);
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bool setup_clos(uint16_t pcpu_id);
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uint64_t clos2pqr_msr(uint16_t clos);
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bool is_platform_rdt_capable(void);
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#endif /* RDT_H */
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