github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-11-13 17:34:12 +00:00
Code Issues Projects Releases Wiki Activity
Files
17c9a4d7bec7c6ab9f69c45516d41e7f9ba404c6
acrn-hypervisor/hypervisor/include/arch/riscv/asm
History
Jian Jun Chen 17c9a4d7be hv: riscv: implement basic logic to bring up APs 
This patch adds the basic logics to bring up all APs in the C
entry of BSP boot. The mapping between logcial CPU IDs and physical
hart IDs is setup based on the pre-generated data from config tool
by parsing the device tree. Logical CPU ID BSP_CPU_ID will always
map to the BSP hart ID. The per pCPU logic ID is saved in tp register.

Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-09-23 11:30:38 +08:00
..
guest
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00
lib
hv: multi-arch add RISC-V bits library implementation
2025-09-22 10:52:06 +08:00
cpu.h
hv: riscv: implement basic logic to bring up APs
2025-09-23 11:30:38 +08:00
init.h
hv: risc-v: add C entry function of BSP and APs
2025-09-15 13:12:21 +08:00
irq.h
…
notify.h
hv: smpcall: riscv: implement SMP call handlers
2025-09-09 16:37:04 +08:00
page.h
enable common code compile
2025-09-19 15:04:55 +08:00
per_cpu.h
hv: riscv: add get/set_pcpu_id and start_pcpus implementation
2025-09-23 11:30:38 +08:00
pgtable.h
[FIXME] hv: riscv: add build dependencies temporarily
2025-09-23 11:30:38 +08:00
qemu.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
sbi.h
hv: riscv: add SBI HSM HART_START interface
2025-09-23 11:30:38 +08:00
security.h
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00
timer.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
vm_config.h
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00