mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-11-14 10:31:59 +00:00
17c9a4d7be
This patch adds the basic logics to bring up all APs in the C entry of BSP boot. The mapping between logcial CPU IDs and physical hart IDs is setup based on the pre-generated data from config tool by parsing the device tree. Logical CPU ID BSP_CPU_ID will always map to the BSP hart ID. The per pCPU logic ID is saved in tp register. Tracked-On: #8791 Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
84 lines
3.1 KiB
C
84 lines
3.1 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#include <types.h>
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#include <lib/util.h>
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#include <debug/logmsg.h>
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#include <board_info.h>
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#include <barrier.h>
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#define cpu_relax() cpu_memory_barrier() /* TODO: replace with yield instruction */
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#define NR_CPUS MAX_PCPU_NUM
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#define LONG_BYTEORDER 3
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#define BYTES_PER_LONG (1 << LONG_BYTEORDER)
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#define BITS_PER_LONG (BYTES_PER_LONG << 3)
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/* Define the interrupt enable bit mask */
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#define SSTATUS_SIE 0x2
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/* Define CPU stack alignment */
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#define CPU_STACK_ALIGN 16UL
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/* In ACRN, struct per_cpu_region is a critical data structure
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* containing key per-CPU data frequently accessed via get_cpu_var().
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* We use the tp register to store the current logical pCPU ID to
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* facilitate efficient per-CPU data access. This design mirrors
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* the x86 implementation, which uses the dedicated MSR_IA32_SYSENTER_CS
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* MSR (unused by the hypervisor) for the same purpose.
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*/
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static inline uint16_t arch_get_pcpu_id(void)
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{
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uint16_t pcpu_id;
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asm volatile ("mv %0, tp" : "=r" (pcpu_id) : : );
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return pcpu_id;
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}
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static inline void arch_set_current_pcpu_id(uint16_t pcpu_id)
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{
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asm volatile ("mv tp, %0" : : "r" (pcpu_id) : "tp");
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}
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static inline void arch_asm_pause(void)
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{
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asm volatile ("pause" ::: "memory");
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}
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/* Write CSR */
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#define cpu_csr_write(reg, csr_val) \
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({ \
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uint64_t val = (uint64_t)csr_val; \
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asm volatile(" csrw " STRINGIFY(reg) ", %0 \n\t" ::"r"(val) : "memory"); \
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})
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/**
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* FIXME: to follow multi-arch design, refactor all of them into static inline functions with corresponding
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* X86 implementation together.
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*/
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#define local_irq_disable() asm volatile("csrc sstatus, %0\n" ::"i"(SSTATUS_SIE) : "memory")
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#define local_irq_enable() asm volatile("csrs sstatus, %0\n" ::"i"(SSTATUS_SIE) : "memory")
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#define local_save_flags(x) ({ asm volatile("csrr %0, sstatus, 0\n" : "=r"(x)::"memory"); })
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#define local_irq_restore(x) ({ asm volatile("csrs sstatus, %0\n" ::"rK"(x & SSTATUS_SIE) : "memory"); })
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#define local_irq_save(x) \
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({ \
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uint32_t val = 0U; \
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asm volatile("csrrc %0, sstatus, 0\n" : "=r"(val) : "i"(SSTATUS_SIE) : "memory"); \
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*(uint32_t *)(x) = val; \
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})
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#define CPU_INT_ALL_DISABLE(x) local_irq_save(x)
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#define CPU_INT_ALL_RESTORE(x) local_irq_restore(x)
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void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
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void init_percpu_hart_id(uint32_t bsp_hart_id);
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uint16_t get_pcpu_id_from_hart_id(uint32_t hart_id);
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#endif /* RISCV_CPU_H */
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