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97a2919138
On some platforms CPUID.0x15:ECX is zero and CPUID.0x16 can
only return the TSC frequency in MHZ which is not accurate.
For example the TSC frequency obtained by CPUID.0x16 is 2300
MHZ and the TSC frequency calibrated by HPET is 2303.998 MHZ
which is much closer to the actual TSC frequency 2304.000 MHZ.
This patch adds the support of using HPET to calibrate TSC
when HPET is available and CPUID.0x15:ECX is zero.
v3->v4:
- move calc_tsc_by_hpet into hpet_calibrate_tsc
v2->v3:
- remove the NULL check in hpet_init
- remove ""& 0xFFFFFFFFU" in tsc_read_hpet
- add comment for the counter wrap in the low 32 bits in
calc_tsc_by_hpet
- use a dedicated function for hpet_calibrate_tsc
v1->v2:
- change native_calibrate_tsc_cpuid_0x15/0x16 to
native_calculate_tsc_cpuid_0x15/0x16
- move hpet_init to BSP init
- encapsulate both HPET and PIT calibration to one function
- revise the commit message with an example"
Tracked-On: #7876
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
52 lines
941 B
C
52 lines
941 B
C
/*
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARCH_X86_TSC_H
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#define ARCH_X86_TSC_H
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#include <types.h>
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#define TSC_PER_MS ((uint64_t)get_tsc_khz())
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/**
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* @brief Read Time Stamp Counter (TSC).
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*
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* @return TSC value
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*/
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static inline uint64_t rdtsc(void)
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{
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uint32_t lo, hi;
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asm volatile("rdtsc" : "=a" (lo), "=d" (hi));
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return ((uint64_t)hi << 32U) | lo;
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}
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/**
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* @brief Get Time Stamp Counter (TSC) frequency in KHz.
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*
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* @return TSC frequency in KHz
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*/
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uint32_t get_tsc_khz(void);
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/**
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* @brief Calibrate Time Stamp Counter (TSC) frequency.
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*
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* @remark Generic time related routines, e.g., cpu_tickrate(), us_to_ticks(),
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* udelay(), etc., relies on this function being called earlier during system initialization.
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*
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* @return None
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*/
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void calibrate_tsc(void);
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/**
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* @brief Initialize HPET.
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*
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* @return None
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*/
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void hpet_init(void);
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#endif /* ARCH_X86_TSC_H */
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