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https://github.com/projectacrn/acrn-hypervisor.git
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8b16be9185
Many of the license and Intel copyright headers include the "All rights reserved" string. It is not relevant in the context of the BSD-3-Clause license that the code is released under. This patch removes those strings throughout the code (hypervisor, devicemodel and misc). Tracked-On: #7254 Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
216 lines
6.7 KiB
C
216 lines
6.7 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef VLAPIC_H
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#define VLAPIC_H
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#include <asm/page.h>
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#include <timer.h>
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#include <asm/apicreg.h>
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/**
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* @file vlapic.h
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*
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* @brief public APIs for virtual LAPIC
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*/
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#define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI
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struct vlapic_timer {
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struct hv_timer timer;
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uint32_t mode;
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uint32_t tmicr;
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uint32_t divisor_shift;
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};
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struct acrn_vlapic {
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/*
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* Please keep 'apic_page' as the first field in
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* current structure, as below alignment restrictions are mandatory
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* to support APICv features:
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* - 'apic_page' MUST be 4KB aligned.
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* IRR, TMR and PIR could be accessed by other vCPUs when deliver
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* an interrupt to vLAPIC.
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*/
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struct lapic_regs apic_page;
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uint32_t vapic_id;
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uint32_t esr_pending;
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int32_t esr_firing;
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struct vlapic_timer vtimer;
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/*
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* isrv: vector number for the highest priority bit that is set in the ISR
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*/
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uint32_t isrv;
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uint64_t msr_apicbase;
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const struct acrn_apicv_ops *ops;
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/*
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* Copies of some registers in the virtual APIC page. We do this for
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* a couple of different reasons:
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* - to be able to detect what changed (e.g. svr_last)
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* - to maintain a coherent snapshot of the register (e.g. lvt_last)
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*/
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uint32_t svr_last;
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uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1];
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} __aligned(PAGE_SIZE);
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struct acrn_vcpu;
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struct acrn_apicv_ops {
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void (*accept_intr)(struct acrn_vlapic *vlapic, uint32_t vector, bool level);
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void (*inject_intr)(struct acrn_vlapic *vlapic, bool guest_irq_enabled, bool injected);
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bool (*has_pending_delivery_intr)(struct acrn_vcpu *vcpu);
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bool (*has_pending_intr)(struct acrn_vcpu *vcpu);
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bool (*apic_read_access_may_valid)(uint32_t offset);
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bool (*apic_write_access_may_valid)(uint32_t offset);
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bool (*x2apic_read_msr_may_valid)(uint32_t offset);
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bool (*x2apic_write_msr_may_valid)(uint32_t offset);
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};
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enum reset_mode;
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extern const struct acrn_apicv_ops *apicv_ops;
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void vlapic_set_apicv_ops(void);
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/**
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* @brief virtual LAPIC
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*
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* @addtogroup acrn_vlapic ACRN vLAPIC
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* @{
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*/
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void vlapic_inject_intr(struct acrn_vlapic *vlapic, bool guest_irq_enabled, bool injected);
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bool vlapic_has_pending_delivery_intr(struct acrn_vcpu *vcpu);
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bool vlapic_has_pending_intr(struct acrn_vcpu *vcpu);
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/**
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* Returns the highest priority pending vector on vLAPIC, or
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* 0 if there is no pending vector.
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*/
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uint32_t vlapic_get_next_pending_intr(struct acrn_vcpu *vcpu);
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/**
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* Clears a pending vector from vIRR. Returns true if
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* the bit was previously present, false otherwise.
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*/
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bool vlapic_clear_pending_intr(struct acrn_vcpu *vcpu, uint32_t vector);
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uint64_t vlapic_get_tsc_deadline_msr(const struct acrn_vlapic *vlapic);
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void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic, uint64_t val_arg);
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uint64_t vlapic_get_apicbase(const struct acrn_vlapic *vlapic);
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int32_t vlapic_set_apicbase(struct acrn_vlapic *vlapic, uint64_t new);
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int32_t vlapic_x2apic_read(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *val);
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int32_t vlapic_x2apic_write(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t val);
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/*
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* Signals to the LAPIC that an interrupt at 'vector' needs to be generated
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* to the 'cpu', the state is recorded in IRR.
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* @pre vcpu != NULL
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* @pre vector <= 255U
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*/
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void vlapic_set_intr(struct acrn_vcpu *vcpu, uint32_t vector, bool level);
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#define LAPIC_TRIG_LEVEL true
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#define LAPIC_TRIG_EDGE false
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static inline uint32_t prio(uint32_t x)
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{
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return (x >> 4U);
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}
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/**
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* @brief Triggers LAPIC local interrupt(LVT).
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*
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* @param[in] vm Pointer to VM data structure
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* @param[in] vcpu_id_arg ID of vCPU, BROADCAST_CPU_ID means triggering
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* interrupt to all vCPUs.
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* @param[in] lvt_index The index which LVT would to be fired.
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*
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* @retval 0 on success.
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* @retval -EINVAL on error that vcpu_id_arg or vector of the LVT is invalid.
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*
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* @pre vm != NULL
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*/
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int32_t vlapic_set_local_intr(struct acrn_vm *vm, uint16_t vcpu_id_arg, uint32_t lvt_index);
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/**
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* @brief Inject MSI to target VM.
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*
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* @param[in] vm Pointer to VM data structure
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* @param[in] addr MSI address.
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* @param[in] data MSI data.
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*
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* @retval 0 on success.
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* @retval -1 on error that addr is invalid.
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*
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* @pre vm != NULL
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*/
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int32_t vlapic_inject_msi(struct acrn_vm *vm, uint64_t addr, uint64_t data);
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void vlapic_receive_intr(struct acrn_vm *vm, bool level, uint32_t dest,
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bool phys, uint32_t delmode, uint32_t vec, bool rh);
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/**
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* @pre vlapic != NULL
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*/
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static inline uint32_t vlapic_get_apicid(const struct acrn_vlapic *vlapic)
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{
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return vlapic->vapic_id;
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}
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void vlapic_create(struct acrn_vcpu *vcpu, uint16_t pcpu_id);
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/*
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* @pre vcpu != NULL
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*/
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void vlapic_free(struct acrn_vcpu *vcpu);
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void vlapic_reset(struct acrn_vlapic *vlapic, const struct acrn_apicv_ops *ops, enum reset_mode mode);
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void vlapic_restore(struct acrn_vlapic *vlapic, const struct lapic_regs *regs);
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uint64_t vlapic_apicv_get_apic_access_addr(void);
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uint64_t vlapic_apicv_get_apic_page_addr(struct acrn_vlapic *vlapic);
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int32_t apic_access_vmexit_handler(struct acrn_vcpu *vcpu);
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int32_t apic_write_vmexit_handler(struct acrn_vcpu *vcpu);
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int32_t veoi_vmexit_handler(struct acrn_vcpu *vcpu);
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void vlapic_update_tpr_threshold(const struct acrn_vlapic *vlapic);
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int32_t tpr_below_threshold_vmexit_handler(struct acrn_vcpu *vcpu);
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uint64_t vlapic_calc_dest_noshort(struct acrn_vm *vm, bool is_broadcast,
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uint32_t dest, bool phys, bool lowprio);
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bool is_x2apic_enabled(const struct acrn_vlapic *vlapic);
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bool is_xapic_enabled(const struct acrn_vlapic *vlapic);
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/**
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* @}
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*/
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/* End of acrn_vlapic */
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#endif /* VLAPIC_H */
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