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https://github.com/projectacrn/acrn-hypervisor.git
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9a7043e83f
ACRN Coding guidelines requires no dead code. Tracked-On: #861 Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com> Reviewed-by: Li, Fei1 <fei1.li@intel.com>
97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
/*-
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* Copyright (c) 2012 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef INSTR_EMUL_H
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#define INSTR_EMUL_H
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#include <types.h>
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#include <cpu.h>
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#include <guest_memory.h>
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struct acrn_vcpu;
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struct instr_emul_vie_op {
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uint8_t op_type; /* type of operation (e.g. MOV) */
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uint16_t op_flags;
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};
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#define VIE_PREFIX_SIZE 4U
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#define VIE_INST_SIZE 15U
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struct instr_emul_vie {
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uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */
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uint8_t num_valid; /* size of the instruction */
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uint8_t num_processed;
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uint8_t addrsize:4, opsize:4; /* address and operand sizes */
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uint8_t rex_w:1, /* REX prefix */
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rex_r:1,
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rex_x:1,
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rex_b:1,
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rex_present:1,
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repz_present:1, /* REP/REPE/REPZ prefix */
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repnz_present:1, /* REPNE/REPNZ prefix */
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opsize_override:1, /* Operand size override */
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addrsize_override:1, /* Address size override */
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seg_override:1; /* Segment override */
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uint8_t mod:2, /* ModRM byte */
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reg:4,
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rm:4;
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uint8_t ss:2, /* SIB byte */
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index:4,
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base:4;
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uint8_t disp_bytes;
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uint8_t imm_bytes;
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uint8_t scale;
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enum cpu_reg_name base_register; /* CPU_REG_xyz */
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enum cpu_reg_name index_register; /* CPU_REG_xyz */
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enum cpu_reg_name segment_register; /* CPU_REG_xyz */
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int64_t displacement; /* optional addr displacement */
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int64_t immediate; /* optional immediate operand */
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uint8_t decoded; /* set to 1 if successfully decoded */
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uint8_t opcode;
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struct instr_emul_vie_op op; /* opcode description */
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uint64_t dst_gpa; /* saved dst operand gpa. Only for movs */
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};
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struct instr_emul_ctxt {
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struct instr_emul_vie vie;
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};
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int32_t emulate_instruction(struct acrn_vcpu *vcpu);
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int32_t decode_instruction(struct acrn_vcpu *vcpu);
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#endif
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